NDLI: SAFER: Stuck-At-Fault Error Recovery for Memories

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Message from the General Co-Chairs

Message from the Program Chair

MICRO 2010 Reviewers

Scalable Speculative Parallelization on Commodity Clusters

Hardware Support for Relaxed Concurrency Control in Transactional Memory

A Dynamically Adaptable Hardware Transactional Memory

ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory

Memory Latency Reduction via Thread Throttling

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Task Superscalar: An Out-of-Order Task Pipeline

Combating Aging with the Colt Duty Cycle Equalizer

SAFER: Stuck-At-Fault Error Recovery for Memories

AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors

Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric

Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies

STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches

Sampling Dead Block Prediction for Last-Level Caches

The ZCache: Decoupling Ways and Associativity

Efficient Selection of Vector Instructions Using Dynamic Programming

Many-Thread Aware Prefetching Mechanisms for GPGPU Applications

Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?

Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels

InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing

Tolerating Concurrency Bugs Using Transactions as Lifeguards

Architectural Support for Fair Reader-Writer Locking

AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection

Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors

Erasing Core Boundaries for Robust and Configurable Performance

Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors

Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches

Understanding the Energy Consumption of Dynamic Random Access Memories

Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory

Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories

Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks

LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support

Throughput-Effective On-Chip Networks for Manycore Accelerators

Adaptive Flow Control for Robust Performance and Energy

ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment

Virtual Snooping: Filtering Snoops in Virtualized Multi-cores

Fractal Coherence: Scalably Verifiable Cache Coherence

A Predictive Model for Dynamic Microarchitectural Adaptivity Control

ReMAP: A Reconfigurable Heterogeneous Multicore Architecture

Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs

Adaptive and Speculative Slack Simulations of CMPs on CMPs

SD3: A Scalable Approach to Dynamic Data-Dependence Profiling

Automatic Parallelization in a Binary Rewriter

Author Index

Roster Page

SAFER: Stuck-At-Fault Error Recovery for Memories

Content Provider	ACM Digital Library
Author	Rivers, Jude A. Lee, Hsien-Hsin S. Srinivasan, Vijayalakshmi Woo, Dong Hyuk Seong, Nak Hee
Abstract	As technology scaling poses a threat to DRAM scaling due to physical limitations such as limited charge, alternative memory technologies including several emerging non-volatile memories are being explored as possible DRAM replacements. One main roadblock for wider adoption of these new memories is the limited write endurance, which leads to wear-out related permanent failures. Furthermore, technology scaling increases the variation in cell lifetime resulting in early failures of many cells. Existing error correcting techniques are primarily devised for recovering from transient faults and are not suitable for recovering from permanent stuck-at faults, which tend to increase gradually with repeated write cycles. In this paper, we propose SAFER, a novel hardware-efficient multi-bit stuck-at fault error recovery scheme for resistive memories, which can function in conjunction with existing wear-leveling techniques. SAFER exploits the key attribute that a failed cell with a stuck-at value is still readable, making it possible to continue to use the failed cell to store data, thereby reducing the hardware overhead for error recovery. SAFER partitions a data block dynamically while ensuring that there is at most one fail bit per partition and uses single error correction techniques per partition for fail recovery. SAFER increases the number of recoverable fails and achieves better lifetime improvement with smaller hardware overhead relative to recently proposed Error Correcting Pointers and even ideal hamming coding scheme.
Starting Page	115
Ending Page	124
Page Count	10
File Format	PDF
ISBN	9780769542997
ISSN	10724451
DOI	10.1109/MICRO.2010.46
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-12-04
Access Restriction	Subscribed
Subject Keyword	Multi-bit error correction stuck-at fault recovery reliability write endurance resistive memory phase-change memory
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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SAFER: Stuck-At-Fault Error Recovery for Memories

Aegis: partitioning data block for efficient recovery of stuck-at-faults in phase change memory.

SAFER: Stuck›At›Fault Error Recovery for Memories

Dynamically replicated memory: building reliable systems from nanoscale resistive memories

RDIS: A recursively defined invertible set scheme to tolerate multiple stuck-at faults in resistive memory

Use ECP, not ECC, for hard failures in resistive memories

Aegis: partitioning data block for efficient recovery of stuck-at-faults in phase change memory

RDIS: Tolerating Many Stuck-At Faults in Resistive Memory

Use ECP, not ECC, for hard failures in resistive memories

SAFER: Stuck-At-Fault Error Recovery for Memories

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