NDLI: AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors

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Message from the General Co-Chairs

Message from the Program Chair

MICRO 2010 Reviewers

Scalable Speculative Parallelization on Commodity Clusters

Hardware Support for Relaxed Concurrency Control in Transactional Memory

A Dynamically Adaptable Hardware Transactional Memory

ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory

Memory Latency Reduction via Thread Throttling

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Task Superscalar: An Out-of-Order Task Pipeline

Combating Aging with the Colt Duty Cycle Equalizer

SAFER: Stuck-At-Fault Error Recovery for Memories

AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors

Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric

Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies

STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches

Sampling Dead Block Prediction for Last-Level Caches

The ZCache: Decoupling Ways and Associativity

Efficient Selection of Vector Instructions Using Dynamic Programming

Many-Thread Aware Prefetching Mechanisms for GPGPU Applications

Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?

Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels

InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing

Tolerating Concurrency Bugs Using Transactions as Lifeguards

Architectural Support for Fair Reader-Writer Locking

AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection

Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors

Erasing Core Boundaries for Robust and Configurable Performance

Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors

Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches

Understanding the Energy Consumption of Dynamic Random Access Memories

Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory

Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories

Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks

LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support

Throughput-Effective On-Chip Networks for Manycore Accelerators

Adaptive Flow Control for Robust Performance and Energy

ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment

Virtual Snooping: Filtering Snoops in Virtualized Multi-cores

Fractal Coherence: Scalably Verifiable Cache Coherence

A Predictive Model for Dynamic Microarchitectural Adaptivity Control

ReMAP: A Reconfigurable Heterogeneous Multicore Architecture

Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs

Adaptive and Speculative Slack Simulations of CMPs on CMPs

SD3: A Scalable Approach to Dynamic Data-Dependence Profiling

Automatic Parallelization in a Binary Rewriter

Author Index

Roster Page

AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors

Content Provider	ACM Digital Library
Author	Eeckhout, Lieven Nair, Arun Arvind John, Lizy Kurian
Abstract	Soft error reliability is increasingly becoming a first-order design concern for microprocessors, as a result of higher transistor counts, shrinking device geometries and lowering of operating voltages. It is important for designers to be able to validate whether the Soft Error Rate (SER) targets of their design have been met, and help end users select the processor best suited to their reliability goals. The knowledge of the observable worst-case SER allows designers to select their design point, and bound the worst-case vulnerability at that design point. We highlight the lack of a methodology for evaluation of the overall observable worst-case SER. Hence, there is a clear need for a so called stress mark that can demonstrably approach the observable worst-case SER. The worst-case thus obtained can be used to identify reliability bottlenecks, validate safety margins used for reliability design and identify inadequacies in benchmark suites used to evaluate SER. Starting from a comprehensive study about how micro architecture-dependent program characteristics affect soft errors, we derive the insights needed to develop an automated and flexible methodology for generating a stress mark that approaches the maximum SER of an out-of-order processor. We demonstrate how our methodology enables architects to quantify the impact of SER-mitigation mechanisms on the worst-case SER of the processor. The stress mark achieves 1.4X higher SER in the core, 2.5X higher SER in DL1 and DTLB, and 1.5X higher SER in L2 as compared to the highest SER induced by SPEC CPU2006 and MiBench programs.
Starting Page	125
Ending Page	136
Page Count	12
File Format	PDF
ISBN	9780769542997
ISSN	10724451
DOI	10.1109/MICRO.2010.34
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-12-04
Access Restriction	Subscribed
Subject Keyword	Avf stressmark soft errors reliability
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors

Avf stressmark: towards an automated methodology for bounding the worst-case vulnerability to soft errors.

2010 43rd annual ieee/acm international symposium on microarchitecture avf stressmark: towards an automated methodology for bounding the worst-case vulnerability to soft errors.

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