NDLI: Proceedings of the 2007 international symposium on Physical design (ISPD '07)

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Cell architecture: key physical design features and methodology

An 8-core, 64-thread, 64-bit power efficient sparc soc (niagara2)

Worst-case delay analysis considering the variability of transistors and interconnects

Rules vs tools: what's the right way to address IC manufacturing complexity?

Carbon nanotube interconnects

X-architecture placement based on effective wire models

Efficient obstacle-avoiding rectilinear steiner tree construction

ISPD placement contest updates and ISPD 2007 global routing contest

The good, the bad, and the statistical

Minimal skew clock embedding considering time variant temperature gradient

Dummy fill density analysis with coupling constraints

Accurate power grid analysis with behavioral transistor network modeling

Optical interconnects: a viable solution for interconnection beyond 10 gbit/sec

A morphing approach to address placement stability

Maze routing steiner trees with effective critical sink optimization

Fear, uncertainty and statistics

An efficent clustering algorithm for low power clock tree synthesis

Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation

Empire: an efficient and compact multiple-parameterized model order reduction method

Mixed-size placement with fixed macrocells using grid-warping

Semi-detailed bus routing with variation reduction

Variation and litho driven physical implementation system

A methodology for interconnect dimension determination

Is your layout density verification exact?: a fast exact algorithm for density calculation

Repeater insertion for concurrent setup and hold time violations with power-delay trade-off

An effective clustering algorithm for mixed-size placement

Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space

A DFM aware, space based router

Pattern sensitive placement for manufacturability

Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors

A stable fixed-outline floorplanning method

Algorithms for automatic length compensation of busses in analog integrated circuits

Proceedings of the 2007 international symposium on Physical design (ISPD '07)

Content Provider	ACM Digital Library
Editor	Pan, David Z. Saxena, P. Chu, C. Chang, Y.-W. Onodera, H. Nam, G.-J. Panda, R. Mains, R. Madden, P. Lienig, J. Madden, Patrick H.
Copyright Year	2007
Abstract	On behalf of the organizing committee for the 2007 International Symposium on Physical Design (ISPD), we would like to extend a warm welcome. This is the $11^{th}$ year of ISPD; from rather humble beginnings as the ACM/SIGDA Physical Design Workshops held intermittently during 1987-1996, the event has evolved into the most competitive forum for the research area. The research community for physical design is not big, but the problems addressed are large. Over the years, many groundbreaking ideas have appeared first at ISPD. The recent interest in benchmarking and open competitions also has roots in ISPD. In earlier years, the perception outside our community was that physical design was simply the shuffling of rectangles to create masks. While the placement of rectangles is certainly a part of our work, modern physical design is much more complex and penetrating. Variability introduced by manufacturing, interconnect delay, and heat dissipation are all tied to the physical layout of a circuit. The papers included in these proceedings reveal many aspects of the physical design problem; as technology marches forwards, physical design tools will have to deal with more and more complex issues. This year's call for papers attracted over 65 submissions of which 22 were accepted. The focus of ISPD attracts only papers that are on topic, so the accepted papers represent the best of the best. In addition to the technical presentations, we have keynote and invited talks that should be of broad interest. We are particularly pleased to have a keynote from IBM's Jim Kahle, Chief Architect of the Cell processor. The general consensus of the VLSI community is that further performance increases from clock scaling are unlikely; power delivery and heat removal are simply too expensive. Parallel computation appears to be the only economical way to improve performance, and the Cell processor is helping to lead the way. The symposium also features a panel discussion by leading experts on "Rules vs. Tools -- What's the right way to address IC manufacturing complexity?" for 45nm and below. It also features special sessions and invited talks on statistical/physical design for manufacturability and the future interconnects. In the prior two years, ISPD has held a placement contest, featuring large benchmarks derived from industrial designs. There are at least a dozen groups around the world who are actively working on placement; this year, the newest results for these benchmarks will be posted. A new contest for global routing is being introduced this year; like the placement contest, we expect a large turnout and fierce competition. The goal of both the placement and routing contests is to set clear objectives for research, and to be able to accurately compare different approaches. While perhaps not as widely known as World Cup Soccer, those involved are just as passionate. The papers from the symposium are available on the ACM Digital Library; slides from most talks for this and prior years are available on the ISPD web site: http://www.ispd.cc.
ISBN	9781595936134
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-03-18
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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