NDLI: A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming

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How will the fabless model survive?

The good, the bad, and the ugly of silicon debug

A CPPLL hierarchical optimization methodology considering jitter, power and locking time

A real time budgeting method for module-level-pipelined bus based system using bus scenarios

Statistical analysis of SRAM cell stability

"The IC nanometer race -- what will it take to win?"

Use of C/C++ models for architecture exploration and verification of DSPs

Charge recycling in MTCMOS circuits: concept and analysis

A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration

Refined statistical static timing analysis through

Entering the hot zone: can you handle the heat and be cool?

Reliability challenges for 45nm and beyond

Power grid physics and implications for CAD

Distributed dynamic BDD reordering

A multi-port current source model for multiple-input switching effects in CMOS library cells

Overview of the MPSoC design challenge

Design of a 125μW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications

Buffer insertion in large circuits with constructive solution search techniques

A flexible and scalable methodology for GHz-speed structural test

Practical methods in coverage-oriented verification of the merom microprocessor

Rapid and low-cost context-switch through embedded processor customization for real-time and control applications

Building a standard ESL design and verification methodology: is it just a dream?

CAD challenges for leading-edge multimedia designs

BoxRouter: a new global router based on box expansion and progressive ILP

Systematic software-based self-test for pipelined processors

Variation-aware analysis: savior of the nanometer era?

A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS

An efficient and versatile scheduling algorithm based on SDC formulation

Design challenges for next-generation multimedia, game and entertainment platforms

Architecture-aware FPGA placement using metric embedding

VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminals

Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability

Energy-scalable OFDM transmitter design and control

Extending the lifetime of fuel cell based hybrid systems

SMERT: energy-efficient design of a multimedia messaging system for mobile devices

Leakage power reduction of embedded memories on FPGAs through location assignment

Solution-processed infrared photovoltaic devices

Synthesis of synchronous elastic architectures

Buffer memory optimization for video codec application modeled in Simulink

Tomorrow's analog: just dead or just different?

NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture

Directed-simulation assisted formal verification of serial protocol and bridge

An IC manufacturing yield model considering intra-die variations

MARS-C: modeling and reduction of soft errors in combinational circuits

Process variation aware OPC with variational lithography modeling

Building a verification test plan: trading brute force for finesse

Electronics beyond nano-scale CMOS

Formal analysis of hardware requirements

Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems

The importance of adopting a package-aware chip design flow

A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18μm CMOS with 5.8GHz ERBW

Efficient simulation of critical synchronous dataflow graphs

Design automation for DNA self-assembled nanostructures

State encoding of large asynchronous controllers

Elmore model for energy estimation in RC trees

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

A multilevel technique for robust and efficient extraction of phase macromodels of digitally controlled oscillators

Clock buffer and wire sizing using sequential programming

DFM: where's the proof of value?

Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification

Unknown-tolerance analysis and test-quality control for test response compaction using space compactors

Constraint-driven floorplan repair

Decision-making for complex SoCs in consumer electronic products

A reconfigurable design-for-debug infrastructure for SoCs

Hierarchical bottom-up analog optimization methodology validated by a delta--sigma A/D converter design for the 802.11a/b/g standard

Exploiting forwarding to improve data bandwidth of instruction-set extensions

Criticality computation in parameterized statistical timing

Maintaining consistency between systemC and RTL system designs

Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions

An automated, reconfigurable, low-power RFID tag

Statistical timing analysis with correlated non-gaussian parameters using independent component analysis

Design tools for reliability analysis

Fast analysis of structured power grid by triangularization based structure preserving model order reduction

SAT sweeping with local observability don't-cares

Statistical logic cell delay analysis using a current-based model

Programming models and HW-SW interfaces abstraction for multi-processor SoC

A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications

Low-power repeater insertion with both delay and slew rate constraints

Timing-based delay test for screening small delay defects

Verification of the cell broadband engine™ processor

Efficient detection and exploitation of infeasible paths for software timing analysis

Steiner network construction for timing critical nets

A test pattern ordering algorithm for diagnosis with truncated fail data

A PLA based asynchronous micropipelining approach for subthreshold circuit design

Register binding for clock period minimization

Efficient SAT-based Boolean matching for FPGA technology mapping

A network security processor design based on an integrated SOC design and test platform

Exploiting K-Distance Signature for Boolean Matching and G-Symmetry Detection

Systematic temperature sensor allocation and placement for microprocessors

High-level power management of embedded systems with application-specific energy cost functions

Signature-based workload estimation for mobile 3D graphics

A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip

Circuits for energy harvesting sensor signal processing

Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint

Configurable cache subsetting for fast cache tuning

Modeling and analysis of circuit performance of ballistic CNFET

Guiding simulation with increasingly refined abstract traces

Novel full-chip gridless routing considering double-via insertion

A design approach for radiation-hard digital electronics

Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits

Are carbon nanotubes the future of VLSI interconnections?

Test generation games from formal specifications

Prediction-based flow control for network-on-chip traffic

Silicon carrier for computer systems

SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers

Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs

Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*

An efficient retiming algorithm under setup and hold constraints

Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM

Exploring compromises among timing, power and temperature in three-dimensional integrated circuits

Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling

Modeling and minimization of PMOS NBTI effect for robust nanometer design

Transistor abstraction for the functional verification of FPGAs

Test response compactor with programmable selector

Optimal cell flipping in placement and floorplanning

Tradeoffs and choices for emerging SoCs in high-end applications

Visibility enhancement for silicon debug

Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration

Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies

Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events

SystemC transaction level models and RTL verification

Physical design methodology of power gating circuits for standard-cell-based design

Design space exploration and prototyping for on-chip multimedia applications

Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty

Design in reliability for communication designs

Stochastic variational analysis of large power grids considering intra-die correlations

Predicate learning and selective theory deduction for a difference logic solver

Multi-shift quadratic alternating direction implicit iteration for high-speed positive-real balanced truncation

System-level exploration tools for MPSoC designs

Hierarchical power distribution and power management scheme for a single chip mobile processor

Fast algorithms for slew constrained minimum cost buffering

Hold time validation on silicon and the relevance of hazards in timing analysis

Shielding against design flaws with field repairable control logic

Leakage-aware intraprogram voltage scaling for embedded processors

Circuit simulation based obstacle-aware Steiner routing

DFT for controlled-impedance I/O buffers

Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing

Towards the automatic exploration of arithmetic-circuit architectures

Optimal simultaneous mapping and clustering for FPGA delay optimization

Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC

Gain-based technology mapping for minimum runtime leakage under input vector uncertainty

HybDTM: a coordinated hardware-software approach for dynamic thermal management

Communication latency aware low power NoC synthesis

Games are up for DVFS

An adaptive FPGA architecture with process variation compensation and reduced leakage

Systems for human-powered mobile computing

Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming

High-performance operating system controlled memory compression

Topology aware mapping of logic functions onto nanowire-based crossbar architectures

Mining global constraints for improving bounded sequential equivalence checking

Optimal jumper insertion for antenna avoidance under ratio upper-bound

A family of cells to reduce the soft-error-rate in ternary-CAM

Computation of accurate interconnect process parameter values for performance corners under process variations

The zen of nonvolatile memories

A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip

4.25 Gb/s laser driver: design challenges and EDA tool limitations

Chameleon ART: a non-optimization based analog design migration framework

GreenBus: a generic interconnect fabric for transaction level modelling

Placement of digital microfluidic biochips using the t-tree formulation

ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling

A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates

Efficient escape routing for hexagonal array of high density I/Os

A robust envelope following method applicable to both non-autonomous and oscillatory circuits

A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures

Automatic invariant strengthening to prove properties in bounded model checking

Fault detection and diagnosis with parity trees for space compaction of test responses

A new LP based incremental timing driven placement for high performance designs

Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery

An up-stream design auto-fix flow for manufacturability enhancement

Towards a C++-based design methodology facilitating sequential equivalence checking

Challenges in sleep transistor design and implementation in low-power designs

Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs

Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools

Practical aspects of reliability analysis for IC designs

A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming

Fast illegal state identification for improving SAT-based induction

A fast passivity test for descriptor systems via structure-preserving transformations of Skew-Hamiltonian/Hamiltonian matrix pencils

Scheduling-based test-case generation for verification of multimedia SoCs

Timing-driven Steiner trees are (practically) free

Timing-constrained and voltage-island-aware voltage assignment

Design space exploration using time and resource duality with the ant colony optimization

Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction

IMPRES: integrated monitoring for processor reliability and security

Gate sizing: finFETs vs 32nm bulk MOSFETs

A systematic method for functional unit power estimation in microprocessors

Optimality study of resource binding with multi-Vdds

Backlight dimming in power-aware mobile displays

FLAW: FPGA lifetime awareness

Harvesting aware power management for sensor networks

Behavior and communication co-optimization for systems with sequential communication media

A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors

A new hybrid FPGA with nanoscale clusters and CMOS routing

Standard cell characterization considering lithography induced variations

DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip

Power-centric design of high-speed I/Os

Ensuring consistency during front-end design using an object-oriented interfacing tool called NETLISP

A framework for embedded system specification under different models of computation in SystemC

A high density, carbon nanotube capacitor for decoupling applications

Budgeting-free hierarchical design method for large scale and high-performance LSIs

Standard cell library optimization for leakage reduction

System level signal and power integrity analysis methodology for system-in-package applications

Lookup table based simulation and statistical modeling of Sigma-Delta ADCs

Reliability modeling and management in dynamic microprocessor-based systems

Fast falsification based on symbolic bounded property checking

Multiple-detect ATPG based on physical neighborhoods

A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction

Model order reduction of linear networks with massive ports via frequency-dependent port packing

Rapid estimation of control delay from high-level specifications

A parallelized way to provide data encryption and integrity checking on a processor-memory bus

DAG-aware AIG rewriting a fresh look at combinational logic synthesis

Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm

Minimization for LED-backlit TFT-LCDs

Synthesis of high-performance packet processing pipelines

Optimizing code parallelization through a constraint network based approach

A model-driven design environment for embedded systems

Variability driven gate sizing for binning yield optimization

Low-power bus encoding using an adaptive hybrid algorithm

PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations

Timing driven power gating

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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