NDLI: Optimizing code parallelization through a constraint network based approach

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Optimizing code parallelization through a constraint network based approach

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Optimizing code parallelization through a constraint network based approach

Content Provider	ACM Digital Library
Author	Chen, Guilin Kandemir, Mahmut Ozturk, Ozcan
Abstract	Increasing employment of chip multiprocessors in embedded computing platforms requires a fresh look at conventional code parallelization schemes. In particular, any compiler-based parallelization scheme for chip multiprocessors should account for the fact that interprocessor communication is cheaper than off-chip memory accesses in these architectures. Based on this observation, this paper proposes a constraint network based approach to code parallelization for chip multiprocessors. Constraint networks have proven to be a useful mechanism for modeling and solving computationally intensive tasks in artificial intelligence. They operate by expressing a problem as a set of variables, variable domains and constraints and define a search procedure that tries to satisfy the constraints (an acceptable subset of them) by assigning values to variables from their specified domains. This paper demonstrates that it is possible to use a constraint network based formulation for the problem of code parallelization for chip multiprocessors. Our experimental evaluation shows that not only a constraint network based approach is feasible for our problem but also highly desirable since it outperforms all other parallelization schemes tested in our experiments.
File Format	PDF
ISBN	1595933816
DOI	10.1145/1146909.1147083
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-07-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Compiler Chip multiprocessing Constraint network
Content Type	Text
Resource Type	Article

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