NDLI: Timing-constrained and voltage-island-aware voltage assignment

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Timing-constrained and voltage-island-aware voltage assignment

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Timing driven power gating

Timing-constrained and voltage-island-aware voltage assignment

Content Provider	ACM Digital Library
Author	Liu, I-Min Wu, Huaizhi Wong, Martin D. F.
Abstract	Multi-Vdd is an effective method to reduce both leakage and dynamic power. A key challenge in a multi-Vdd design is to limit the design cost and the demand for level shifters. This can be tackled by grouping cells of different supply voltages into a small number of voltage islands. Recently, an elegant algorithm [7] is proposed for generating voltage islands that balance the power versus design cost tradeoff under performance requirement, according to the placement proximity of the critical cells. One prerequisite of [7] is an initial voltage assignment at the standard cell level that meets timing. In this paper, we present a novel method to produce quality voltage assignment to [7], which not only meets timing but also forms good proximity of the critical cells to provide [7] with a smooth input. The algorithm is based on effective delay budgeting and efficient computation of physical proximity by Voronoi diagram. Our extensive experiments on real industrial designs show that our algorithm leads to 25% - 75% improvement in the voltage island generation, with the computation time only linear to the design size.
Starting Page	429
Ending Page	432
Page Count	4
File Format	PDF
ISBN	1595933816
DOI	10.1145/1146909.1147023
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-07-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Voronoi diagram Voltage assignment Low power Timing
Content Type	Text
Resource Type	Article

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