NDLI: Reducing Design Complexity of the Load/Store Queue

Please wait, while we are loading the content...

Message from the General Chair

Message from the Program Chair

Committees

Reviewers

Microarchitecture on the MOSFET Diet

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power

A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor

TLC: Transmission Line Caches

Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures

Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches

Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction

Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data

Power-driven Design of Router Microarchitectures in On-chip Networks

Optimum Power/Performance Pipeline Depth

Processor Acceleration Through Automated Instruction Set Customization

The Reconfigurable Streaming Vector Processor (RSVPTM)

Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice

In Memory of Bob Rau

Generational Cache Management of Code Traces in Dynamic Optimization Systems

The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System

IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium®-based systems

LLVA: A Low-level Virtual Instruction Set Architecture

Comparing Program Phase Detection Techniques

Using Interaction Costs for Microarchitectural Bottleneck Analysis

Fast Path-Based Neural Branch Prediction

Hardware Support for Control Transfers in Code Caches

Exploiting Value Locality in Physical Register Files

Macro-op Scheduling: Relaxing Scheduling Loop Constraints

WaveScalar

Universal Mechanisms for Data-Parallel Architectures

Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors

Instruction Replication for Clustered Microarchitectures

Efficient Memory Integrity Verification and Encryption for Secure Processors

Fast Secure Processor for Inhibiting Software Piracy and Tampering

IPStash: a Power-Efficient Memory Architecture for IP-lookup

Design and Implementation of High-Performance Memory Systems for Future Packet Buffers

Beating in-order stalls with "flea-flicker" two-pass pipelining

Scalable Hardware Memory Disambiguation for High ILP Processors

Reducing Design Complexity of the Load/Store Queue

Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors

Author Index

Reducing Design Complexity of the Load/Store Queue

Content Provider	ACM Digital Library
Author	Vijaykumar, T. N. Ooi, Chong Liang Park, Il
Abstract	With faster CPU clocks and wider pipelines, all relevantmicroarchitecture components should scale accordingly.There have been many proposals for scaling the issue queue,register file, and cache hierarchy. However, nothing has beendone for scaling the load/store queue, despite the increasingpressure on the load/store queue in terms of capacity andsearch bandwidth. The load/store queue is a CAM structurewhich holds in-flight memory instructions and supportssimultaneous searches to honor memory dependencies andmemory consistency models. Therefore, it is difficult to scalethe load/store queue.In this study, we introduce novel techniques to scale theload/store queue. We propose two techniques, store-loadpair predictor and load buffer, to reduce the search bandwidthrequirement; and one technique, segmentation, toscale the size. We show that a load/store queue using ourpredictor and load buffer needs only one port to outperforma conventional two-ported load/store queue. Compared tothe same base case, segmentation alone achieves speedupsof 5% for integer benchmarks and 19% for floating pointbenchmarks. A one-ported load/store queue using all of ourtechniques improves performance on average by 6% and23%, and up to 15% and 59%, for integer and floating-pointbenchmarks, respectively, over a two-ported conventionalload/store queue.
File Format	PDF
ISBN	076952043X
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-12-03
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Reducing Design Complexity of the Load/Store Queue (2003)

Reducing Design Complexity of the Load/Store Queue (2003)

Reducing design complexity of the load/store queue

Reducing data cache energy consumption via cached load/store queue

Power-efficient and scalable load/store queue design via address compression

Reducing data cache energy consumption via cached load/store queue

Load-store queue management: an energy-efficient design based on a state-filtering mechanism ∗.

NoSQ: Store-Load Communication without a Store Queue

A Power-Efficient and Scalable Load-Store Queue Design (2005)

Reducing Design Complexity of the Load/Store Queue

Similar Documents

Reducing Design Complexity of the Load/Store Queue (2003)

Reducing Design Complexity of the Load/Store Queue (2003)

Reducing design complexity of the load/store queue

Reducing data cache energy consumption via cached load/store queue

Power-efficient and scalable load/store queue design via address compression

Reducing data cache energy consumption via cached load/store queue

Load-store queue management: an energy-efficient design based on a state-filtering mechanism ∗.

NoSQ: Store-Load Communication without a Store Queue

A Power-Efficient and Scalable Load-Store Queue Design (2005)

Reducing Design Complexity of the Load/Store Queue