NDLI: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

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Microarchitecture on the MOSFET Diet

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power

A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor

TLC: Transmission Line Caches

Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures

Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches

Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction

Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data

Power-driven Design of Router Microarchitectures in On-chip Networks

Optimum Power/Performance Pipeline Depth

Processor Acceleration Through Automated Instruction Set Customization

The Reconfigurable Streaming Vector Processor (RSVPTM)

Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice

In Memory of Bob Rau

Generational Cache Management of Code Traces in Dynamic Optimization Systems

The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System

IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium®-based systems

LLVA: A Low-level Virtual Instruction Set Architecture

Comparing Program Phase Detection Techniques

Using Interaction Costs for Microarchitectural Bottleneck Analysis

Fast Path-Based Neural Branch Prediction

Hardware Support for Control Transfers in Code Caches

Exploiting Value Locality in Physical Register Files

Macro-op Scheduling: Relaxing Scheduling Loop Constraints

WaveScalar

Universal Mechanisms for Data-Parallel Architectures

Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors

Instruction Replication for Clustered Microarchitectures

Efficient Memory Integrity Verification and Encryption for Secure Processors

Fast Secure Processor for Inhibiting Software Piracy and Tampering

IPStash: a Power-Efficient Memory Architecture for IP-lookup

Design and Implementation of High-Performance Memory Systems for Future Packet Buffers

Beating in-order stalls with "flea-flicker" two-pass pipelining

Scalable Hardware Memory Disambiguation for High ILP Processors

Reducing Design Complexity of the Load/Store Queue

Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors

Author Index

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Content Provider	ACM Digital Library
Author	Ernst, Dan Das, Shidhartha Rao, Rajeev Mudge, Trevor Kim, Nam Sung Blaauw, David Ziesler, Conrad Pham, Toan Austin, Todd Pant, Sanjay Flautner, Krisztian
Abstract	With increasing clock frequencies and silicon integration,power aware computing has become a critical concernin the design of embedded processors and systems-on-chip.One of the more effective and widely used methods for power-awarecomputing is dynamic voltage scaling (DVS). In orderto obtain the maximum power savings from DVS, it is essentialto scale the supply voltage as low as possible while ensuringcorrect operation of the processor. The critical voltage ischosen such that under a worst-case scenario of process andenvironmental variations, the processor always operates correctly.However, this approach leads to a very conservativesupply voltage since such a worst-case combination of differentvariabilities will be very rare. In this paper, we propose anew approach to DVS, called Razor, based on dynamic detectionand correction of circuit timing errors. The key idea ofRazor is to tune the supply voltage by monitoring the errorrate during circuit operation, thereby eliminating the need forvoltage margins and exploiting the data dependence of circuitdelay. A Razor flip-flop is introduced that double-samplespipeline stage values, once with a fast clock and again with atime-borrowing delayed clock. A metastability-tolerant comparatorthen validates latch values sampled with the fastclock. In the event of a timing error, a modified pipeline mispeculationrecovery mechanism restores correct programstate. A prototype Razor pipeline was designed in 0.18 µmtechnology and was analyzed. Razor energy overheads duringnormal operation are limited to 3.1%. Analyses of a full-custommultiplier and a SPICE-level Kogge-Stone addermodel reveal that substantial energy savings are possible forthese devices (up to 64.2%) with little impact on performancedue to error recovery (less than 3%).
File Format	PDF
ISBN	076952043X
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-12-03
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Razor: a low-power pipeline based on circuit-level timing speculation

1 razor: a low-power pipeline based on circuit- level timing speculation 1.1 reference (2007).

Summary Part 2 Razor : A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Razor: a low-power pipeline based on circuit-level timing speculation

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation (2003)

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Identifying and predicting timing-critical instructions to boost timing speculation

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Similar Documents

Razor: a low-power pipeline based on circuit-level timing speculation

1 razor: a low-power pipeline based on circuit- level timing speculation 1.1 reference (2007).

Summary Part 2 Razor : A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Razor: a low-power pipeline based on circuit-level timing speculation

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation (2003)

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Identifying and predicting timing-critical instructions to boost timing speculation

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation