NDLI: A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor

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A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor

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A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor

Content Provider	ACM Digital Library
Author	Weaver, Christopher Emer, Joel Austin, Todd Reinhardt, Steven K. Mukherjee, Shubhendu S.
Abstract	Single-event upsets from particle strikes have become akey challenge in microprocessor design. Techniques todeal with these transient faults exist, but come at a cost.Designers clearly require accurate estimates of processorerror rates to make appropriate cost/reliability trade-offs.This paper describes a method for generating theseestimates.A key aspect of this analysis is that some single-bit faults(such as those occurring in the branch predictor) will notproduce an error in a program's output. We define astructure's architectural vulnerability factor (AVF) as theprobability that a fault in that particular structure willresult in an error. A structure's error rate is the product ofits raw error rate, as determined by process and circuittechnology, and the AVF.Unfortunately, computing AVFs of complex structures,such as the instruction queue, can be quite involved. Weidentify numerous cases, such as prefetches, dynamicallydead code, and wrong-path instructions, in which a faultwill not affect correct execution. We instrument a detailedIA64 processor simulator to map bit-level microarchitecturalstate to these cases, generating per-structure AVFestimates. This analysis shows AVFs of 28% and 9% forthe instruction queue and execution units, respectively,averaged across dynamic sections of the entire CPU2000benchmark suite.
File Format	PDF
ISBN	076952043X
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-12-03
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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