NDLI: The block-based trace cache

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Volume 27, Issue 5, Dec. 1999

Volume 27, Issue 4, Sept. 1999

Volume 27, Issue 3, June 1999

Volume 27, Issue 2, May 1999

Dynamic vectorization

Speculation techniques for improving load related instruction scheduling

Correlated load-address predictors

Selective value prediction

Tolerating late memory traps in ILP processors

Memory forwarding

Decoupling local variable accesses in a wide-issue superscalar processor

Effective jump-pointer prefetching for linked data structures

Performance of image and video processing with general-purpose processors and media ISA extensions

A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization

Commit-reconcile & fences (CRF)

Is SC + ILP = RC?

Memory sharing predictor

Simultaneous subordinate microthreading (SSMT)

The block-based trace cache

The program decision logic approach to predicated execution

A performance comparison of contemporary DRAM architectures

A scalable front-end architecture for fast instruction delivery

Area efficient architectures for information integrity in cache memories

Value prediction in VLIW machines

Storageless value prediction using prior register values

Using network interface support to avoid asynchronous protocol processing in shared virtual memory systems

Multicast snooping

Scaling application performance on a cache-coherent multiprocessor

Volume 27, Issue 1, March 1999

The block-based trace cache

Content Provider	ACM Digital Library
Author	Black, Bryan Shen, John Paul Rychlik, Bohuslav
Abstract	The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-based trace cache implementation that can achieve higher IPC performance with more efficient storage of traces. Instead of explicitly storing instructions of a trace, pointers to blocks constituting a trace are stored in a much smaller trace table. The block-based trace cache renames fetch addresses at the basic block level and stores aligned blocks in a block cache. Traces are constructed by accessing the replicated block cache using block pointers from the trace table. Performance potential of the block-based trace cache is quantified and compared with perfect branch prediction and perfect fetch schemes. Comparing to the conventional trace cache, the block-based design can achieve higher IPC, with less impact on cycle time.Results: Using the SPECint95 benchmarks, a 16-wide realistic design of a block-based trace cache can improve performance 75% over a baseline design and to within 7% of a baseline design with perfect branch prediction. With idealized trace prediction, it is shown the block-based trace cache with an 1K-entry block cache achieves the same performance of the conventional trace cache with 32K entries.
Starting Page	196
Ending Page	207
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/307338.300996
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	27
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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