NDLI: Is SC + ILP = RC?

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Volume 27, Issue 5, Dec. 1999

Volume 27, Issue 4, Sept. 1999

Volume 27, Issue 3, June 1999

Volume 27, Issue 2, May 1999

Dynamic vectorization

Speculation techniques for improving load related instruction scheduling

Correlated load-address predictors

Selective value prediction

Tolerating late memory traps in ILP processors

Memory forwarding

Decoupling local variable accesses in a wide-issue superscalar processor

Effective jump-pointer prefetching for linked data structures

Performance of image and video processing with general-purpose processors and media ISA extensions

A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization

Commit-reconcile & fences (CRF)

Is SC + ILP = RC?

Memory sharing predictor

Simultaneous subordinate microthreading (SSMT)

The block-based trace cache

The program decision logic approach to predicated execution

A performance comparison of contemporary DRAM architectures

A scalable front-end architecture for fast instruction delivery

Area efficient architectures for information integrity in cache memories

Value prediction in VLIW machines

Storageless value prediction using prior register values

Using network interface support to avoid asynchronous protocol processing in shared virtual memory systems

Multicast snooping

Scaling application performance on a cache-coherent multiprocessor

Volume 27, Issue 1, March 1999

Is SC + ILP = RC?

Content Provider	ACM Digital Library
Author	Vijaykumar, T. N. Falsafi, Babak Gniady, Chris
Abstract	Sequential consistency (SC) is the simplest programming interface for shared-memory systems but imposes program order among all memory operations, possibly precluding high performance implementations. Release consistency (RC), however, enables the highest performance implementations but puts the burden on the programmer to specify which memory operations need to be atomic and in program order. This paper shows, for the first time, that SC implementations can perform as well as RC implementations if the hardware provides enough support for speculation. Both SC and RC implementations rely on reordering and overlapping memory operations for high performance. To enforce order when necessary, an RC implementation uses software guarantees, whereas an SC implementation relies on hardware speculation. Our SC implementation, called SC++, closes the performance gap because: (1) the hardware allows not just loads, as some current SC implementations do, but also stores to bypass each other speculatively to hide remote latencies, (2) the hardware provides large speculative state for not just processor, as previously proposed, but also memory to allow out-of-order memory operations, (3) the support for hardware speculation does not add excessive overheads to processor pipeline critical paths, and (4) well-behaved applications incur infrequent rollbacks of speculative execution. Using simulation, we show that SC++ achieves an RC implementation's performance in all the six applications we studied.
Starting Page	162
Ending Page	171
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/307338.300993
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	27
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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