NDLI: Selective eager execution on the PolyPath architecture

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Volume 26, Issue 5, Dec. 1998

Volume 26, Issue 4, September 1998

Volume 26, Issue 3, June 1998

Memory system characterization of commercial workloads

Performance characterization of a Quad Pentium Pro SMP using OLTP workloads

Execution characteristics of desktop applications on Windows NT

An analysis of database workload performance on simultaneous multithreaded processors

An analysis of correlation and predictability

Branch prediction based on universal data compression algorithms

Modeling program predictability

Multi-level texture caching for 3D graphics hardware

Declustered disk array architectures with optimal and near-optimal parallelism

Confidence estimation for speculation control

Pipeline gating

Memory dependence prediction using store sets

Dynamic history-length fitting

Accurate indirect branch prediction

Using prediction to accelerate coherence protocols

Increasing TLB reach using superpages backed by shadow memory

Options for dynamic address translation in COMAs

Integrated predicated and speculative execution in the IMPACT EPIC architecture

Threaded multiple path execution

Selective eager execution on the PolyPath architecture

Improving trace cache effectiveness with branch promotion and trace packing

The effect of instruction fetch bandwidth on value prediction

Dynamic IPC/clock rate optimization

Performance modeling and code partitioning for the DS architecture

Exploiting fine-grain thread level parallelism on the MIT multi-ALU processor

Effects of architectural and technological advances on the HP/Convex Exemplar's memory and communication performance

Design choices in the SHRIMP system

Flexible use of memory for replication/migration in cache-coherent DSM multiprocessors

Exploiting spatial locality in data caches using spatial footprints

Low load latency through sum-addressed memory (SAM)

Analytic evaluation of shared-memory systems with ILP processors

Volume 26, Issue 2, May 1998

Volume 26, Issue 1, March 1998

Selective eager execution on the PolyPath architecture

Content Provider	ACM Digital Library
Author	Paithankar, Abhijit Klauser, Artur Grunwald, Dirk
Abstract	Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an execution model to overcome mis-speculation penalties by executing both paths after diffident branches. We present the micro-architecture of the PolyPath processor, which is an extension of an aggressive superscalar, out-of-order architecture. The PolyPath architecture uses a novel instruction tagging and register renaming mechanism to execute instructions from multiple paths simultaneously in the same processor pipeline, while retaining maximum resource availability for single-path code sequences.Results of our execution-driven, pipeline-level simulations show that SEE can improve performance by as much as 36% for the go benchmark, and an average of 14% on SPECint95, when compared to a normal superscalar, out-of-order, speculative execution, monopath processor. Moreover, our architectural model is both elegant and practical to implement, using a small amount of additional state and control logic.
Starting Page	250
Ending Page	259
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/279361.279393
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	26
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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