NDLI: Multi-level texture caching for 3D graphics hardware

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Volume 26, Issue 5, Dec. 1998

Volume 26, Issue 4, September 1998

Volume 26, Issue 3, June 1998

Memory system characterization of commercial workloads

Performance characterization of a Quad Pentium Pro SMP using OLTP workloads

Execution characteristics of desktop applications on Windows NT

An analysis of database workload performance on simultaneous multithreaded processors

An analysis of correlation and predictability

Branch prediction based on universal data compression algorithms

Modeling program predictability

Multi-level texture caching for 3D graphics hardware

Declustered disk array architectures with optimal and near-optimal parallelism

Confidence estimation for speculation control

Pipeline gating

Memory dependence prediction using store sets

Dynamic history-length fitting

Accurate indirect branch prediction

Using prediction to accelerate coherence protocols

Increasing TLB reach using superpages backed by shadow memory

Options for dynamic address translation in COMAs

Integrated predicated and speculative execution in the IMPACT EPIC architecture

Threaded multiple path execution

Selective eager execution on the PolyPath architecture

Improving trace cache effectiveness with branch promotion and trace packing

The effect of instruction fetch bandwidth on value prediction

Dynamic IPC/clock rate optimization

Performance modeling and code partitioning for the DS architecture

Exploiting fine-grain thread level parallelism on the MIT multi-ALU processor

Effects of architectural and technological advances on the HP/Convex Exemplar's memory and communication performance

Design choices in the SHRIMP system

Flexible use of memory for replication/migration in cache-coherent DSM multiprocessors

Exploiting spatial locality in data caches using spatial footprints

Low load latency through sum-addressed memory (SAM)

Analytic evaluation of shared-memory systems with ILP processors

Volume 26, Issue 2, May 1998

Volume 26, Issue 1, March 1998

Multi-level texture caching for 3D graphics hardware

Content Provider	ACM Digital Library
Author	Cox, Michael Shantz, Michael Bhandari, Narendra
Abstract	Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval of texture during rasterization, and the application is responsible for managing this memory. The push architecture has a bandwidth advantage, but disadvantages of limited texture capacity, escalation of accelerator memory requirements (and therefore cost), and poor memory utilization. The push architecture also requires the programmer to solve the bin- packing problem of managing accelerator memory each frame. More recently graphics hardware on PC-class machines has moved to an implementation of what we call the pull architecture. Texture is stored in system memory and downloaded by the accelerator as needed. The pull architecture has advantages of texture capacity, stems the escalation of accelerator memory requirements, and has good memory utilization. It also frees the programmer from accelerator texture memory management. However, the pull architecture suffers escalating requirements for bandwidth from main memory to the accelerator. In this paper we propose multi-level texture caching to provide the accelerator with the bandwidth advantages of the push architecture combined with the capacity advantages of the pull architecture. We have studied the feasibility of 2-level caching and found the following: (1) significant re-use of texture between frames; (2) L2 caching requires significantly less memory than the push architecture; (3) L2 caching requires significantly less bandwidth from host memory than the pull architecture; (4) L2 caching enables implementation of smaller L1 caches that would otherwise bandwidth-limit accelerators on the workloads in this paper. Results suggest that an L2 cache achieves the original advantage of the pull architecture --- stemming the growth of local texture memory --- while at the same time stemming the current explosion in demand for texture bandwidth between host memory and the accelerator.
Starting Page	86
Ending Page	97
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/279361.279372
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	26
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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