NDLI: An analysis of database workload performance on simultaneous multithreaded processors

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Volume 26, Issue 5, Dec. 1998

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Memory system characterization of commercial workloads

Performance characterization of a Quad Pentium Pro SMP using OLTP workloads

Execution characteristics of desktop applications on Windows NT

An analysis of database workload performance on simultaneous multithreaded processors

An analysis of correlation and predictability

Branch prediction based on universal data compression algorithms

Modeling program predictability

Multi-level texture caching for 3D graphics hardware

Declustered disk array architectures with optimal and near-optimal parallelism

Confidence estimation for speculation control

Pipeline gating

Memory dependence prediction using store sets

Dynamic history-length fitting

Accurate indirect branch prediction

Using prediction to accelerate coherence protocols

Increasing TLB reach using superpages backed by shadow memory

Options for dynamic address translation in COMAs

Integrated predicated and speculative execution in the IMPACT EPIC architecture

Threaded multiple path execution

Selective eager execution on the PolyPath architecture

Improving trace cache effectiveness with branch promotion and trace packing

The effect of instruction fetch bandwidth on value prediction

Dynamic IPC/clock rate optimization

Performance modeling and code partitioning for the DS architecture

Exploiting fine-grain thread level parallelism on the MIT multi-ALU processor

Effects of architectural and technological advances on the HP/Convex Exemplar's memory and communication performance

Design choices in the SHRIMP system

Flexible use of memory for replication/migration in cache-coherent DSM multiprocessors

Exploiting spatial locality in data caches using spatial footprints

Low load latency through sum-addressed memory (SAM)

Analytic evaluation of shared-memory systems with ILP processors

Volume 26, Issue 2, May 1998

Volume 26, Issue 1, March 1998

An analysis of database workload performance on simultaneous multithreaded processors

Content Provider	ACM Digital Library
Author	Barroso, Luiz André Lo, Jack L. Eggers, Susan J. Parekh, Sujay S. Levy, Henry M. Gharachorloo, Kourosh
Abstract	Simultaneous multithreading (SMT) is an architectural technique in which the processor issues multiple instructions from multiple threads each cycle. While SMT has been shown to be effective on scientific workloads, its performance on database systems is still an open question. In particular, database systems have poor cache performance, and the addition of multithreading has the potential to exacerbate cache conflicts.This paper examines database performance on SMT processors using traces of the Oracle database management system. Our research makes three contributions. First, it characterizes the memory-system behavior of database systems running on-line transaction processing and decision support system workloads. Our data show that while DBMS workloads have large memory footprints, there is substantial data reuse in a small, cacheable "critical" working set. Second, we show that the additional data cache conflicts caused by simultaneous multithreaded instruction scheduling can be nearly eliminated by the proper choice of software-directed policies for virtual-to-physical page mapping and per-process address offsetting. Our results demonstrate that with the best policy choices, D-cache miss rates on an 8-context SMT are roughly equivalent to those on a single-threaded superscalar. Multithreading also leads to better interthread instruction cache sharing, reducing I-cache miss rates by up to 35%. Third, we show that SMT's latency tolerance is highly effective for database applications. For example, using a memory-intensive OLTP workload, an 8-context SMT processor achieves a 3-fold increase in instruction throughput over a single-threaded superscalar with similar resources.
Starting Page	39
Ending Page	50
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/279361.279367
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	26
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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