NDLI: Wire Delay is Not a Problem for SMT (In the Near Future)

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Volume 32, Issue 5, December 2004

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General Co-Chair's Message

Program Chair's Message

Evaluation of the Raw Microprocessor

Evaluating the Imagine Stream Architecture

Field-testing IMPACT EPIC research results in Itanium 2

Wire Delay is Not a Problem for SMT (In the Near Future)

The Vector-Thread Architecture

Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance

Microarchitecture Optimizations for Exploiting Memory-Level Parallelism

Memory Ordering

Transactional Memory Coherence and Consistency

A Formal Approach to Frequent Energy Adaptations for Multimedia Applications

Power Awareness through Selective Dynamically Optimized Traces

Low-Latency Virtual-Channel Routers for On-Chip Networks

Adaptive Cache Compression for High-Performance Processors

From Sequences of Dependent Instructions to Functions

Prophet/Critic Hybrid Branch Prediction

Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor

The Case for Lifetime Reliability-Aware Microprocessors

Exploiting Resonant Behavior to Reduce Inductive Noise

Use-Based Register Caching with Decoupled Indexing

A Content Aware Integer Register File Organization

Physical Register Inlining

A First-Order Superscalar Processor Model

Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies

Extended Split-Issue

A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy

Volume 32, Issue 1, March 2004

Wire Delay is Not a Problem for SMT (In the Near Future)

Content Provider	ACM Digital Library
Author	Vijaykumar, T. N. Chishti, Zeshan
Abstract	Previous papers have shown that the slow scaling of wiredelays compared to logic delays will prevent superscalar performancefrom scaling with technology.In this paper we showthat the optimal pipeline for superscalar becomes shallowerwith technology, when wire delays are considered, tighteningprevious results that deeper pipelines perform only as well asshallower pipelines.The key reason for the lack of performancescaling is that superscalar does not have sufficient parallelismto hide the relatively-increased wire delays.However,Simultaneous Multithreading (SMT) provides the much-neededparallelism.We show that an SMT running a multiprogrammedworkload with just 4-way issue not only retains theoptimal pipeline depth over technology generations, enablingat least 43% increase in clock speed every generation, but alsoachieves the remainder of the expected speedup of two pergeneration through IPC.As wire delays become more dominantin future technologies, the number of programs needs tobe scaled modestly to maintain the scaling trends, at least tillthe near-future 50nm technology.While this result ignoresbandwidth constraints, using SMT to tolerate latency due towire delays is not that simple because SMT causes bandwidthproblems.Most of the stages of a modern out-of-order-issuepipeline employ RAM and CAM structures.Wire delays in conventional,latency-optimized RAM/CAM structures preventthem from being pipelined in a scaled manner.We show thatthis limitation prevents scaling of SMT throughput.We use bitlinescaling to allow RAM/CAM bandwidth to scale with technology.Bitline scaling enables SMT throughput to scale at therate of two per technology generation in the near future.
File Format	PDF
ISSN	01635964
DOI	10.1145/1028176.1006706
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	32
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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