NDLI: Prophet/Critic Hybrid Branch Prediction

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Volume 32, Issue 5, December 2004

Volume 32, Issue 4, September 2004

Volume 32, Issue 3, June 2004

Volume 32, Issue 2, March 2004

General Co-Chair's Message

Program Chair's Message

Evaluation of the Raw Microprocessor

Evaluating the Imagine Stream Architecture

Field-testing IMPACT EPIC research results in Itanium 2

Wire Delay is Not a Problem for SMT (In the Near Future)

The Vector-Thread Architecture

Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance

Microarchitecture Optimizations for Exploiting Memory-Level Parallelism

Memory Ordering

Transactional Memory Coherence and Consistency

A Formal Approach to Frequent Energy Adaptations for Multimedia Applications

Power Awareness through Selective Dynamically Optimized Traces

Low-Latency Virtual-Channel Routers for On-Chip Networks

Adaptive Cache Compression for High-Performance Processors

From Sequences of Dependent Instructions to Functions

Prophet/Critic Hybrid Branch Prediction

Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor

The Case for Lifetime Reliability-Aware Microprocessors

Exploiting Resonant Behavior to Reduce Inductive Noise

Use-Based Register Caching with Decoupled Indexing

A Content Aware Integer Register File Organization

Physical Register Inlining

A First-Order Superscalar Processor Model

Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies

Extended Split-Issue

A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy

Volume 32, Issue 1, March 2004

Prophet/Critic Hybrid Branch Prediction

Content Provider	ACM Digital Library
Author	Ramirez, Alex Lai, Konrad Valero, Mateo Falcon, Ayose Stark, Jared
Abstract	This paper introduces the prophet/critic hybrid conditionalbranch predictor, which has two component predictorsthat play the role of either prophet or critic.Theprophet is a conventional predictor that uses branch historyto predict the direction of the current branch.Further accessesof the prophet yield predictions for the branches followingthe current one.Predictions for the current branchand the ones that follow are collectively known as thebranch's future.They are actually a prophecy, or predictedbranch future.The critic uses both the branch's history andfuture to give a critique of the prophet's prediction fo thecurrent branch.The critique, either agree or disagree, isused to generate the final prediction for the branch.Our results show an 8K + 8K byte prophet/critic hybridhas 39% fewer mispredicts than a 16K byte 2Bc-gskewpredictor-a predictor similar to that of the proposed CompaqAlpha EV8 processor-across a wide range of applications.The distance between pipeline flushes due to mispredictsincreases from one flush per 418 micro-operations(uops) to one per 680 uops.For gcc, the percentage of mispredictedbranches drops from 3.11% to 1.23%.On a machinebased on the Intel® Pentium® 4 processor, this improvesuPC (Uops Per Cycle) by 7.8% (18% for gcc) andreduces the number of uops fetched (along both correct andincorrect paths) by 8.6%.
File Format	PDF
ISSN	01635964
DOI	10.1145/1028176.1006722
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	32
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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