NDLI: High-bandwidth address translation for multiple-issue processors

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Volume 24, Issue 5, Dec. 1996

Volume 24, Issue 4, Sept. 1996

Volume 24, Issue 3, June 1 1996

Volume 24, Issue 2, May 1996

Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches

An analysis of dynamic branch prediction schemes on system workloads

Correlation and aliasing in dynamic branch predictors

Decoupled hardware support for distributed shared memory

Evaluation of design alternatives for a multiprocessor microprocessor

Memory bandwidth limitations of future microprocessors

Missing the memory wall

Don't use the page number, but a pointer to it

The difference-bit cache

Understanding application performance on shared virtual memory systems

Application and architectural bottlenecks in large scale distributed shared memory machines

Increasing cache port efficiency for dynamic superscalar microprocessors

High-bandwidth address translation for multiple-issue processors

DCD—disk caching disk

Polling watchdog

Exploiting choice

Evaluation of multithreaded uniprocessors for commercial application environments

Performance comparison of ILP machines with cycle time evaluation

Rotating combined queueing (RCQ)

A router architecture for real-time point-to-point networks

Coherent network interfaces for fine-grain communication

Informing memory operations

Instruction prefetching of systems codes with layout optimized for reduced cache misses

Compiler and hardware support for cache coherence in large-scale multiprocessors

Early experience with message-passing on the SHRIMP multicomputer

Volume 24, Issue 1, March 1996

High-bandwidth address translation for multiple-issue processors

Content Provider	ACM Digital Library
Author	Sohi, Gurindar S. Austin, Todd M.
Abstract	In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing bandwidth demands on the address translation mechanism. Most current microprocessor designs meet this demand with a multi-ported TLB. While this design provides an excellent hit rate at each port, its access latency and area grow very quickly as the number of ports is increased. As bandwidth demands continue to increase, multi-ported designs will soon impact memory access latency.We present four high-bandwidth address translation mechanisms with latency and area characteristics that scale better than a multiported TLB design. We extend traditional high-bandwidth memory design techniques to address translation, developing interleaved and multi-level TLB designs. In addition, we introduce two new designs crafted specifically for high-bandwidth address translation. Piggyback ports are introduced as a technique to exploit spatial locality in simultaneous translation requests, allowing accesses to the same virtual memory page to combine their requests at the TLB access port. Pretranslation is introduced as a technique for attaching translations to base register values, making it possible to reuse a single translation many times.We perform extensive simulation-based studies to evaluate our designs. We vary key system parameters, such as processor model, page size, and number of architected registers, to see what effects these changes have on the relative merits of each approach. A number of designs show particular promise. Multi-level TLBs with as few as eight entries in the upper-level TLB nearly achieve the performance of a TLB with unlimited bandwidth. Piggyback ports combined with a lesser-ported TLB structure, e.g., an interleaved or multi-ported TLB, also perform well. Pretranslation over a single-ported TLB performs almost as well as a same-sized multi-level TLB with the added benefit of decreased access latency for physically indexed caches.
Starting Page	158
Ending Page	167
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/232974.232990
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	24
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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