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High-bandwidth address translation for multiple-issue processors (1996)
| Content Provider | CiteSeerX |
|---|---|
| Author | Austin, Todd M. Sohi, Gurindar S. |
| Description | In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing bandwidth demands on the address translation mechanism. Most current microprocessor designs meet this demand with a multi-ported TLB. While this design provides an excellent hit rate at each port, its access latency and area grow very quickly as the number of ports is increased. As bandwidth demands continue to increase, multi-ported designs will soon impact memory access latency. We present four high-bandwidth address translation mechanisms with latency and area characteristics that scale better than a multiported TLB design. We extend traditional high-bandwidth memory design techniques to address translation, developing interleaved and multi-level TLB designs. In addition, we introduce two new designs crafted specifically for high-bandwidth address translation. Piggyback ports are introduced as a technique to exploit spatial locality in simultaneous translation requests, allowing accesses to the same virtual memory page to combine their requests at the TLB access port. Pretranslation is introduced as a technique for attaching translations to base register values, making it possible to reuse a single translation many times. We perform extensive simulation-based studies to evaluate our designs. We vary key system parameters, such as processor model, page size, and number of architected registers, to see what effects these changes have on the relative merits of each approach. A number of designs show particular promise. Multi-level TLBs with as few as eight entries in the upper-level TLB nearly achieve the performance of a TLB with unlimited bandwidth. Piggyback ports combined with a lesser-ported TLB structure, e.g., an interleaved or multi-ported TLB, also perform well. Pretranslation over a singleported TLB performs almost as well as a same-sized multi-level TLB with the added benefit of decreased access latency for physically indexed caches. 1 |
| File Format | |
| Language | English |
| Publisher Date | 1996-01-01 |
| Publisher Institution | in Proc. of the 23rd Annual International Symposium on Computer Architecture |
| Access Restriction | Open |
| Subject Keyword | Bandwidth Demand Multi-level Tlbs Area Characteristic Excellent Hit Rate Multi-ported Tlb Multi-ported Design Indexed Cache Microprocessor Design Memory Access Latency Extensive Simulation-based Study System Performance Lesser-ported Tlb Structure Multiple-issue Processor Register Value Unlimited Bandwidth Address Translation Mechanism Architected Register Single Translation Many Time Virtual Memory Page Decreased Access Latency Piggyback Port Simultaneous Translation Request Traditional High-bandwidth Memory Design Technique Processor Model Spatial Locality Multi-level Tlb Design Instruction-level Parallelism New Design Key System Parameter High-bandwidth Address Translation Mechanism Multiported Tlb Design Upper-level Tlb Same-sized Multi-level Tlb Tlb Access Port Singleported Tlb Performs Relative Merit Page Size Current Microprocessor Particular Promise High-bandwidth Address Translation Added Benefit Access Latency |
| Content Type | Text |
| Resource Type | Article |
