NDLI: Informing memory operations:providing memory performance feedback in modern processors

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Volume 24, Issue 5, Dec. 1996

Volume 24, Issue 4, Sept. 1996

Volume 24, Issue 3, June 1 1996

Volume 24, Issue 2, May 1996

Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches

An analysis of dynamic branch prediction schemes on system workloads

Correlation and aliasing in dynamic branch predictors

Decoupled hardware support for distributed shared memory

Evaluation of design alternatives for a multiprocessor microprocessor

Memory bandwidth limitations of future microprocessors

Missing the memory wall

Don't use the page number, but a pointer to it

The difference-bit cache

Understanding application performance on shared virtual memory systems

Application and architectural bottlenecks in large scale distributed shared memory machines

Increasing cache port efficiency for dynamic superscalar microprocessors

High-bandwidth address translation for multiple-issue processors

DCD—disk caching disk

Polling watchdog

Exploiting choice

Evaluation of multithreaded uniprocessors for commercial application environments

Performance comparison of ILP machines with cycle time evaluation

Rotating combined queueing (RCQ)

A router architecture for real-time point-to-point networks

Coherent network interfaces for fine-grain communication

Informing memory operations

Instruction prefetching of systems codes with layout optimized for reduced cache misses

Compiler and hardware support for cache coherence in large-scale multiprocessors

Early experience with message-passing on the SHRIMP multicomputer

Volume 24, Issue 1, March 1996

Informing memory operations:providing memory performance feedback in modern processors

Content Provider	ACM Digital Library
Author	Martonosi, Margaret Mowry, Todd C. Horowitz, Mark Smith, Michael D.
Abstract	Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to address this problem successfully in specific situations. However, the generality of these software approaches has been limited because current architectures do not provide a fine-grained, low-overhead mechanism for observing and reacting to memory behavior directly. To fill this need, we propose a new class of memory operations called informing memory operations, which essentially consist of a memory operation combined (either implicitly or explicitly) with a conditional branch-and-link operation that is taken only if the reference suffers a cache miss. We describe two different implementations of informing memory operations---one based on a cache-outcome condition code and another based on low-overhead traps---and find that modern in-order-issue and out-of-order-issue superscalar processors already contain the bulk of the necessary hardware support. We describe how a number of software-based memory optimizations can exploit informing memory operations to enhance performance, and look at cache coherence with fine-grained access control as a case study. Our performance results demonstrate that the runtime overhead of invoking the informing mechanism on the Alpha 21164 and MIPS R10000 processors is generally small enough to provide considerable flexibility to hardware and software designers, and that the cache coherence application has improved performance compared to other current solutions. We believe that the inclusion of informing memory operations in future processors may spur even more innovative performance optimizations.
Starting Page	260
Ending Page	270
Page Count	11
File Format	PDF
ISSN	01635964
DOI	10.1145/232974.233000
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	24
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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