NDLI: Compiler and hardware support for cache coherence in large-scale multiprocessors:design considerations and performance study

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Volume 24, Issue 5, Dec. 1996

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Volume 24, Issue 3, June 1 1996

Volume 24, Issue 2, May 1996

Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches

An analysis of dynamic branch prediction schemes on system workloads

Correlation and aliasing in dynamic branch predictors

Decoupled hardware support for distributed shared memory

Evaluation of design alternatives for a multiprocessor microprocessor

Memory bandwidth limitations of future microprocessors

Missing the memory wall

Don't use the page number, but a pointer to it

The difference-bit cache

Understanding application performance on shared virtual memory systems

Application and architectural bottlenecks in large scale distributed shared memory machines

Increasing cache port efficiency for dynamic superscalar microprocessors

High-bandwidth address translation for multiple-issue processors

DCD—disk caching disk

Polling watchdog

Exploiting choice

Evaluation of multithreaded uniprocessors for commercial application environments

Performance comparison of ILP machines with cycle time evaluation

Rotating combined queueing (RCQ)

A router architecture for real-time point-to-point networks

Coherent network interfaces for fine-grain communication

Informing memory operations

Instruction prefetching of systems codes with layout optimized for reduced cache misses

Compiler and hardware support for cache coherence in large-scale multiprocessors

Early experience with message-passing on the SHRIMP multicomputer

Volume 24, Issue 1, March 1996

Compiler and hardware support for cache coherence in large-scale multiprocessors:design considerations and performance study

Content Provider	ACM Digital Library
Author	Choi, Lynn Yew, Pen-Chung
Abstract	In this paper, we study a hardware-supported, compiler directed (HSCD) cache coherence scheme, which can be implemented on a large-scale multiprocessor using off-the-shelf microprocessors, such as the Cray T3D. It can be adapted to various cache organizations, including multi-word cache lines and byte-addressable architectures. Several system related issues, including critical sections, inter-thread communication, and task migration have also been addressed. The cost of the required hardware support is small and proportional to the cache size. The necessary compiler algorithms, including intra- and interprocedural array data-flow analysis, have been implemented on the Polaris compiler [17].From our simulation study using the Perfect Club benchmarks, we found that, in spite of the conservative analysis made by the compiler, the performance of the proposed HSCD scheme can be comparable to that of a full-map hardware directory scheme. With its comparable performance and reduced hardware cost, the scheme can be a viable alternative for large-scale multiprocessors, such as the Cray T3D, that rely on users to maintain data coherence.
Starting Page	283
Ending Page	294
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/232974.233002
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	24
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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