NDLI: Decoupled hardware support for distributed shared memory

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Volume 24, Issue 5, Dec. 1996

Volume 24, Issue 4, Sept. 1996

Volume 24, Issue 3, June 1 1996

Volume 24, Issue 2, May 1996

Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches

An analysis of dynamic branch prediction schemes on system workloads

Correlation and aliasing in dynamic branch predictors

Decoupled hardware support for distributed shared memory

Evaluation of design alternatives for a multiprocessor microprocessor

Memory bandwidth limitations of future microprocessors

Missing the memory wall

Don't use the page number, but a pointer to it

The difference-bit cache

Understanding application performance on shared virtual memory systems

Application and architectural bottlenecks in large scale distributed shared memory machines

Increasing cache port efficiency for dynamic superscalar microprocessors

High-bandwidth address translation for multiple-issue processors

DCD—disk caching disk

Polling watchdog

Exploiting choice

Evaluation of multithreaded uniprocessors for commercial application environments

Performance comparison of ILP machines with cycle time evaluation

Rotating combined queueing (RCQ)

A router architecture for real-time point-to-point networks

Coherent network interfaces for fine-grain communication

Informing memory operations

Instruction prefetching of systems codes with layout optimized for reduced cache misses

Compiler and hardware support for cache coherence in large-scale multiprocessors

Early experience with message-passing on the SHRIMP multicomputer

Volume 24, Issue 1, March 1996

Decoupled hardware support for distributed shared memory

Content Provider	ACM Digital Library
Author	Pfile, Robert W. Wood, David A. Reinhardt, Steven K.
Abstract	This paper investigates hardware support for fine-grain distributed shared memory (DSM) in networks of workstations. To reduce design time and implementation cost relative to dedicated DSM systems, we decouple the functional hardware components of DSM support, allowing greater use of off-the-shelf devices.We present two decoupled systems, Typhoon-0 and Typhoon-1. Typhoon-0 uses an off-the-shelf protocol processor and network interface; a custom access control device is the only DSM-specific hardware. To demonstrate the feasibility and simplicity of this access control device, we designed and built an FPGA-based version in under one year. Typhoon-1 also uses an off-the-shelf protocol processor, but integrates the network interface and access control devices for higher performance.We compare the performance of the two decoupled systems with two integrated systems via simulation. For six benchmarks on 32 nodes, Typhoon-0 ranges from 30% to 309% slower than the best integrated system, while Typhoon-1 ranges from 13% to 132% slower. Four of the six benchmarks achieve speedups of 12 to 18 on Typhoon-0 and 15 to 26 on Typhoon-1, compared with 19 to 35 on the best integrated system. Two benchmarks are hampered by high communication overheads, but selectively replacing shared-memory operations with message passing provides speedups of at least 16 on both decoupled systems. These speedups indicate that decoupled designs can potentially provide a cost-effective alternative to complex high-end DSM systems.
Starting Page	34
Ending Page	43
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/232974.232979
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	24
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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