NDLI: Ultra-low-power adder stage design for exascale floating point units

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Ultra-low-power adder stage design for exascale floating point units

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Ultra-low-power adder stage design for exascale floating point units

Content Provider	ACM Digital Library
Author	Bagherzadeh, Nader Hermida, Román Del barrio, Alberto A.
Copyright Year	2014
Abstract	Currently, the most powerful supercomputers can provide tens of petaflops. Future many-core systems are estimated to provide an exaflop. However, the power budget limitation makes these machines still unfeasible and unaffordable. Floating Point Units (FPUs) are critical from both the power consumption and performance points of view of today's microprocessors and supercomputers. Literature offers very different designs. Some of them are focused on increasing performance no matter the penalty, and others on decreasing power at the expense of lower performance. In this article, we propose a novel approach for reducing the power of the FPU without degrading the rest of parameters. Concretely, this power reduction is also accompanied by an area reduction and a performance improvement. Hence, an overall energy gain will be produced. According to our experiments, our proposed unit consumes 17.5%, 23% and 16.5% less energy for single, double and quadruple precision, with an additional 15%, 21.5% and 14.5% delay reduction, respectively. Furthermore, area is also diminished by 4%, 4.5 and 5%.
Starting Page	1
Ending Page	24
Page Count	24
File Format	PDF
ISSN	15399087
e-ISSN	15583465
DOI	10.1145/2567932
Volume Number	13
Issue Number	3s
Journal	ACM Transactions on Embedded Computing Systems (TECS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-03-28
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Floating point unit Multiply accumulation Multispeculation
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Software

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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