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| Content Provider | ACM Digital Library |
|---|---|
| Author | Nguyen, Trung Duc Van Meter, Rodney |
| Copyright Year | 2014 |
| Abstract | Reversible logic has applications in low-power computing and quantum computing. However, there are few existing designs for reversible floating-point adders and none suitable for quantum computation. In this article, we propose a resource-efficient reversible floating-point adder, suitable for binary quantum computation, improving the design of Nachtigal et al. [2011]. Our work focuses on improving the reversible designs of the alignment unit and the normalization unit, which are the most expensive parts. By changing a few elements of the existing algorithm, including the circuit designs of the RLZC (reversible leading zero counter) and converter, we have reduced the cost by about 68%. We also propose quantum designs adapted to use gates from fault-tolerant libraries. The $\textit{KQ}$ for our fault-tolerant design is almost 60 times as expensive as for a 32-bit fixed-point addition. We note that the floating-point representation makes in-place, truly reversible arithmetic impossible, requiring us to retain both inputs, which limits the sustainability of its use for quantum computation. |
| Starting Page | 1 |
| Ending Page | 18 |
| Page Count | 18 |
| File Format | |
| ISSN | 15504832 |
| e-ISSN | 15504840 |
| DOI | 10.1145/2629525 |
| Journal | ACM Journal on Emerging Technologies in Computing Systems (JETC) |
| Volume Number | 11 |
| Issue Number | 2 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2014-11-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | IEEE-754 specification Reversible circuit Floating-point arithmetic Low-power computing Nano technology Quantum computing |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture Nanoscience and Nanotechnology Software |
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