NDLI: HARS: A hardware-assisted runtime software for embedded many-core architectures

Content Provider	ACM Digital Library
Author	Lhuillier, Yves David, Raphaël Guerre, Alexandre Jaber, Chafic Ojail, Maroun Philippe, Jean-Marc Chehida, Karim Ben Andriamisaina, Caaliph Thabet, Farhat
Copyright Year	2014
Abstract	The current trend in embedded computing consists in increasing the number of processing resources on a chip. Following this paradigm, cluster-based many-core accelerators with a shared hierarchical memory have emerged. Handling synchronizations on these architectures is critical since parallel implementations speed-ups of embedded applications strongly depend on the ability to exploit the largest possible number of cores while limiting task management overhead. This article presents the combination of a low-overhead complete runtime software and a flexible hardware accelerator for synchronizations called HARS (Hardware-Assisted Runtime Software). Experiments on a multicore test chip showed that the hardware accelerator for synchronizations has less than 1% area overhead compared to a cluster of the chip while reducing synchronization latencies (up to 2.8 times compared to a $\textit{test-and-set}$ implementation) and contentions. The runtime software part offers basic features like memory management but also optimized execution engines to allow the easy and efficient extraction of the parallelism in applications with multiple programming models. By using the hardware acceleration as well as a very low overhead task scheduling software technique, we show that HARS outperforms an optimized state-of-the-art task scheduler by 13% for the execution of a parallel application.
Starting Page	1
Ending Page	25
Page Count	25
File Format	PDF
ISSN	15399087
e-ISSN	15583465
DOI	10.1145/2517311
Volume Number	13
Issue Number	3s
Journal	ACM Transactions on Embedded Computing Systems (TECS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-03-28
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Embedded runtime software Hardware acceleration Many-core architectures Multicore architectures
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Throughput-driven synthesis of embedded software for pipelined execution on multicore architectures

Embedded Multiprocessor Systems-on-Chip Programming

Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators

SPMPool: Runtime SPM Management for Memory-Intensive Applications in Embedded Many-Cores

IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures

A Cache Tuning Heuristic for Multicore Architectures

Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors

SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization

Investigation on AUTOSAR-Compliant Solutions for Many-Core Architectures

HARS: A hardware-assisted runtime software for embedded many-core architectures

Similar Documents

Throughput-driven synthesis of embedded software for pipelined execution on multicore architectures

Embedded Multiprocessor Systems-on-Chip Programming

Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators

SPMPool: Runtime SPM Management for Memory-Intensive Applications in Embedded Many-Cores

IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures

A Cache Tuning Heuristic for Multicore Architectures

Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors

SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization

Investigation on AUTOSAR-Compliant Solutions for Many-Core Architectures

HARS: A hardware-assisted runtime software for embedded many-core architectures