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| Content Provider | ACM Digital Library |
|---|---|
| Author | Foglia, Pierfrancesco Solinas, Marco |
| Copyright Year | 2014 |
| Abstract | Improvements in semiconductor nanotechnology made chip multiprocessors the reference architecture for high-performance microprocessors. CMPs usually adopt large Last-Level Caches (LLC) shared among cores and private L1 caches, whose performances depend on the wire-delay dominated response time of LLC. NUCA (NonUniform Cache Architecture) caches represent a viable solution for tolerating wire-delay effects. In this article, we present Re-NUCA, a NUCA cache that exploits replication of blocks inside the LLC to avoid performance limitations of D-NUCA caches due to conflicting access to shared data. Results show that a Re-NUCA LLC permits to improve performances of more than 5% on average, and up to 15% for applications that strongly suffer from conflicting access to shared data, while reducing network traffic and power consumption with respect to D-NUCA caches. Besides, it outperforms different S-NUCA schemes optimized with victim replication. |
| Starting Page | 1 |
| Ending Page | 23 |
| Page Count | 23 |
| File Format | |
| ISSN | 15399087 |
| e-ISSN | 15583465 |
| DOI | 10.1145/2566568 |
| Volume Number | 13 |
| Issue Number | 3s |
| Journal | ACM Transactions on Embedded Computing Systems (TECS) |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2014-03-28 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Multicore NUCA Block replication Cache memory |
| Content Type | Text |
| Resource Type | Article |
| Subject | Hardware and Architecture Software |
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