NDLI: Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems

Content Provider	Springer Nature Link
Author	Gaona, Epifanio Titos Gil, J. Rubén Fernández, Juan Acacio, Manuel E.
Copyright Year	2013
Abstract	In the search for new paradigms to simplify multithreaded programming, Transactional Memory (TM) is currently being advocated as a promising alternative to deadlock-prone lock-based synchronization. In this way, future many-core CMP architectures may need to provide hardware support for TM. On the other hand, power dissipation constitutes a first class consideration in multicore processor designs. In this work, we propose Selective Dynamic Serialization (SDS) as a new technique to improve energy consumption without degrading performance in applications with conflicting transactions by avoiding wasted work due to aborted transactions. Our proposal, which is implemented on top of a hardware transactional memory (HTM) system with an eager conflict management policy, detects and serializes conflicting transactions dynamically (at run-time). In its simplest form, in case of conflict, one transaction is allowed to continue whilst the rest are completely stalled. Once the executing transaction has finished, it wakes up several of the stalling transactions. More elaborated implementations of SDS try to delay this behavior until serialization of transactions is profitable, achieving the best trade-off between performance, energy savings and network traffic. SDS implementations differ from each other in the condition that triggers the serialization mode. We have evaluated several SDS schemes using GEMS, a full-system simulator implementing the LogTM-SE Eager–Eager HTM system, and several benchmarks from the STAMP suite. Results for a 16-core CMP show that SDS obtains reductions of 6 % on average in energy consumption (more than 20 % in high contention scenarios) in a wide range of benchmarks without affecting, on average, execution time. At the same time, network traffic level is also reduced by 22 %.
Starting Page	914
Ending Page	934
Page Count	21
File Format	PDF
ISSN	09208542
Journal	The Journal of Supercomputing
Volume Number	68
Issue Number	2
e-ISSN	15730484
Language	English
Publisher	Springer US
Publisher Date	2013-12-22
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Many-core CMPs Hardware transactional memory Transactions Run-time serialization Energy consumption Execution time Programming Languages, Compilers, Interpreters Processor Architectures Computer Science
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

DASC-DIR: a low-overhead coherence directory for many-core processors

Fast and efficient commits for Lazy-Lazy hardware transactional memory

Languages, Compilers and Run-Time Systems for Scalable Computers

Performance scalability and energy consumption on distributed and many-core platforms

Leveraging irrevocability to deal with signature saturation in hardware transactional memory

Improving performance of software transactional memory through contention locality

Dual-execution mode processor architecture

Software transactional memories: an approach for multicore programming

Performance–energy adaptation of parallel programs in pervasive computing

Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems

Similar Documents

DASC-DIR: a low-overhead coherence directory for many-core processors

Fast and efficient commits for Lazy-Lazy hardware transactional memory

Languages, Compilers and Run-Time Systems for Scalable Computers

Performance scalability and energy consumption on distributed and many-core platforms

Leveraging irrevocability to deal with signature saturation in hardware transactional memory

Improving performance of software transactional memory through contention locality

Dual-execution mode processor architecture

Software transactional memories: an approach for multicore programming

Performance–energy adaptation of parallel programs in pervasive computing

Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems