NDLI: Customized pipeline and instruction set architecture for embedded processing engines

Content Provider	Springer Nature Link
Author	Yazdanbakhsh, Amir Salehi, Mostafa E. Fakhraie, Sied Mehdi
Copyright Year	2014
Abstract	Custom instructions potentially improve execution speed and code compression of embedded applications. However, more efficient custom instructions need higher number of simultaneous registerfile accesses. Larger registerfiles are more power hungry with complex forwarding interconnects. Therefore, due to the limited ports of the base processor registerfile, size and efficiency of custom instructions could be generally limited. Recent researches have focused on overcoming this limitation by some innovative architectural techniques supplemented with customized compilations. However, to the best of our knowledge there are few researches that take into account the complete pipeline design and implementation considerations. This paper proposes a customized instruction set and pipeline architecture for an optimized embedded engine. The proposed architecture increases the performance by enhancing the available registerfile data bandwidth through register access pipelining. The achieved improvements are made by introducing double-word custom instructions whose registerfile accesses are overlapped in the pipeline. Potential hazards in such instructions are resolved by the introduced pipeline backwarding concept, yielding higher performance and code compression. While we study the effectiveness of the proposed architecture on domain-specific workloads from packet-processing benchmarks, the developed framework and architecture are applicable to other embedded application domains.
Starting Page	948
Ending Page	977
Page Count	30
File Format	PDF
ISSN	09208542
Journal	The Journal of Supercomputing
Volume Number	68
Issue Number	2
e-ISSN	15730484
Language	English
Publisher	Springer US
Publisher Date	2014-02-06
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Embedded packet-processing engine Customized application-specific processor Custom instruction generation Area performance tradeoffs Custom instruction data bandwidth Programming Languages, Compilers, Interpreters Processor Architectures Computer Science
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Hardware and Architecture Software

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