NDLI: NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits’ Life Time

Content Provider	Springer Nature Link
Author	Copetti, T. Cardoso Medeiros, G. Bolzani Poehls, L. Vargas, F.
Copyright Year	2016
Abstract	Advances in CMOS technology have made possible the increase of integrated circuit’s density, which impacts directly on the circuit’s performance. However, technology scaling poses some reliability concerns that directly affect the circuit’s lifetime. One of the most important issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). This phenomenon increases the threshold voltage of pMOS transistors, which introduces delay along the integrated circuits’ paths, eventually causing functional failures. In this paper, a hardware-based technique able to increase the lifetime of Integrated Circuits (ICs) is proposed. In more detail, the technique is based on an on-chip sensor able to monitor IC’s aging and to adjust its power supply voltage in order to minimize NBTI effects and increase the circuit’s lifetime. Experimental results obtained throughout simulations demonstrate the technique’s efficiency, since the circuit’s lifetime has been increased by 150 %. Finally, the analysis of the main overheads introduced as well as the impact related to process variation renders the evaluation of the proposed approach possible.
Starting Page	315
Ending Page	328
Page Count	14
File Format	PDF
ISSN	09238174
Journal	Journal of Electronic Testing
Volume Number	32
Issue Number	3
e-ISSN	15730727
Language	English
Publisher	Springer US
Publisher Date	2016-05-16
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	NBTI On-chip sensor Process variation Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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