NDLI: Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability

Content Provider	Springer Nature Link
Author	Villacorta, Hector Segura, Jaume Champac, Victor
Copyright Year	2016
Abstract	FinFET technology has become the most promising alternative to continue CMOS scaling due to its improved short channel effects. Design flexibility reduces on FinFET based circuits such as SRAM cells due to the effective channel width is determined by an integer number of fins. In this work, the impact of fin height size of FinFET transistors on the simultaneous behavior of soft error sensitivity and SRAM cell static noise margin is investigated. 3-D TCAD Sentarus environment is used to quantify the amount of collected and critical charges of an SRAM cell due to a heavy ion strike while Mix-Mode Hspice-TCAD simulation is used for stability analysis. Even more, the influence of process variations on sensitivity to soft errors and cell stability is considered. A 10 nm-SOI Tri-Gate FinFET technology is used. Results show that increasing the fin height of FinFET transistors considerably increases SRAM cell sensitivity to soft errors but improves its stability. This suggests that the optimum fin height value of FinFET transistors of an SRAM cell depends on the best tradeoff between soft error robustness and stability.
Starting Page	307
Ending Page	314
Page Count	8
File Format	PDF
ISSN	09238174
Journal	Journal of Electronic Testing
Volume Number	32
Issue Number	3
e-ISSN	15730727
Language	English
Publisher	Springer US
Publisher Date	2016-05-10
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	FinFET Soft errors Static noise margin Process variations Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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