NDLI: NBTI-aware design of integrated circuits: a hardware-based approach

Content Provider	IEEE Xplore Digital Library
Author	Copetti, T. Cardoso Medeiros, G. Bolzani Poehls, L. Vargas, F.
Copyright Year	2015
Description	Author affiliation: PUCRS, Porto Alegre, Brazil (Copetti, T.; Cardoso Medeiros, G.; Bolzani Poehls, L.; Vargas, F.)
Abstract	Advances in CMOS technology have made possible the increase of integrated circuit's density, which impacts directly on the performance of the circuit. However, technology scaling poses some reliability concerns. One of the main issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). This phenomenon increases the threshold voltage of pMOS transistors, which introduces delay along the integrated circuits' paths, eventually causing functional failures. In this paper, a hardware-based technique able to increase the lifetime of integrated circuits is proposed. In more detail, the technique is based on an on-chip sensor able to monitor integrated circuit aging and to adjust the supply voltage of the circuit in order to minimize NBTI effects. Experimental results obtained throughout simulations demonstrate the technique's efficiency. Finally, an analysis of the overheads as well as the impact related to process variation renders the evaluation of the proposed approach possible.
Starting Page	1
Ending Page	6
File Size	549448
Page Count	6
File Format	PDF
ISBN	9781467367103
DOI	10.1109/LATW.2015.7102525
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-25
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Degradation Actuators on-chip sensor Aging Delays Integrated circuit modeling NBTI Monitoring Flip-flops
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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