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Asynchronous sequential circuit design using pass transistor iterative logic arrays
| Content Provider | Semantic Scholar |
|---|---|
| Author | Liu, Muye N. Maki, Gary K. Whitaker, Sterling R. |
| Copyright Year | 1991 |
| Abstract | The Iterative Logic Array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19940013903.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
