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Low Power Multiplier Design Using Complementary Pass-Transistor Asynchronous Adiabatic Logic
| Content Provider | Semantic Scholar |
|---|---|
| Author | Kumar, A. Kishore Bosch, Robert |
| Copyright Year | 2010 |
| Abstract | In this paper, low power multiplier design using complementary pass-transistor asynchronous adiabatic logic is investigated. Adiabatic circuits are very low power circuits compared with CMOS logic circuits, provided the Power Clock Generators consumes less power and mutilate all low power advantages from the adiabatic logic by consuming large portion of the total power in the clock generation circuitry (1, 2). Also clock routing is major challenge in the adiabatic, because of routing-delay between the gates. To get out of the problems related to clock generation and synchronous clock routing, a new solution namely asynchronous adiabatic logic (5) is used. Here we have designed, simulated a multiplier with Complementary Pass- Transistor Asynchronous Adiabatic Logic (CPTAAL) which exhibits low power and reliable logical operations comprising the benefit of both asynchronous systems with adiabatic benefits. Compared with the conventional CMOS implementation, this design achieves energy savings from 50% to 74% for clock rates ranging from 100MHz to 300MHz. Moore's law describes the requirement of the transistors for VLSI design; it gives the empirical observation that component density and performance of integrated circuits, doubles every year, which was then revised to doubling every two years. With the help of the scaling rules set by Dennard, smart optimization can be achieved by means of timely introduction of new processing techniques in device structures, and materials (9). To overcome the power and area requirements of the computational complexities, the dimensions of transistors are shrunk into the deep sub-micron region and predominantly handled by process engineering. Driven by tremendous advances in lithography, the 65nm process technology node featuring approximately 32nm transistors is in vogue right now in high volume production. Moreover the technology migration has become much costly for process the design in terms of its physical design. Developers are forced to bare the tool cost in order to achieve the low power requirements. The transistor cost versus lithographic tool cost is given in the silicon technology future road map, it is noted that transistor cost has decreased seven orders of magnitude whereas tool cost has increased. Thus, the alternate method or migration of process engineering is most invited. The internal capacitance and resistance of transistor structure are shown in Figure 1. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.enggjournals.com/ijcse/doc/IJCSE10-02-07-64.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
