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Asynchronous sequential circuit design using pass transistor iterative logic arrays
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Whitaker, S. R. Maki, G. K. Liu, M. N. |
| Copyright Year | 1991 |
| Description | The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations. |
| File Size | 769246 |
| Page Count | 14 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19940013903 |
| Archival Resource Key | ark:/13960/t0tr0tb83 |
| Language | English |
| Publisher Date | 1991-01-01 |
| Access Restriction | Open |
| Subject Keyword | Electronics And Electrical Engineering State Vectors Theorems Logic Circuits Circuit Reliability Very Large Scale Integration Logic Design Architecture Computers Design Analysis Modularity Crossovers Transistor Logic Switching Circuits Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Article |
