Loading...
Please wait, while we are loading the content...
Similar Documents
ASIC implementation of high efficiency 8-bit 'OctaLynx' RISC microprocessor
| Content Provider | Semantic Scholar |
|---|---|
| Author | Frankiewicz, Maciej Gal, Ryszard Golda, Adam Brzozowski, Ireneusz |
| Copyright Year | 2012 |
| Abstract | The paper presents structure of 8-bit RISC microcontroller with 16-bit address bus called OctaLynx. The processor behavior is described by Verilog hardware description language and was fabricated as ASIC in CMOS LF 0.15 μm (1.8 V) technology. Before fabrication FPGA tests were run. The integrated circuit consists of the core and some peripherals (8-bit general purpose input-output ports, timers/counters, USART, SPI).The controller was designed for tests of the dynamic power management systems. |
| Starting Page | 241 |
| Ending Page | 253 |
| Page Count | 13 |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://bambus.iel.waw.pl/pliki/ogolne/prace%20IEL/260/19_ang.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
