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Design and Implementation of Asynchronous 8-bit Microprocessor
| Content Provider | Semantic Scholar |
|---|---|
| Author | Kim, Kyung Ki |
| Copyright Year | 2017 |
| Abstract | A delay-insensitive asynchronous design methodology, named NULL Convention Logic (NCL), is one of mainstream asynchronous design techniques for low-power robust circuit operation. It offers many advantages over synchronous circuit design having scaling issues in nanometer region such as severe process variations, short channel effects, aging effects, and etc. Therefore, this paper proposes a new design methodology to convert synchronous circuits into NCL circuits in RTL (register transfer level) and a new interfacing block to connect NCL circuits to synchronous circuits/memories or synchronous circuits/memories to NCL circuits. In this paper, the proposed methodology has been evaluated by an 8051 microprocessor designed using a standard 0.35um CMOS technology, and the experimental results show that the proposed asynchronous 8051 microprocessor reduces power consumption by 40% compared with a synchronous 8051 microprocessor. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.ripublication.com/ijaer17/ijaerv12n7_08.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
