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Novel Design of 32-bit Asynchronous (RISC) Microprocessor & its Implementation on FPGA
| Content Provider | Semantic Scholar |
|---|---|
| Author | Rani, A. Meena Grover, Naresh |
| Copyright Year | 2018 |
| Abstract | As the efficiency and power consumption plays an important role in electronic system design, an asynchronous design is used to reduce such challenges faced in synchronous architectures. The asynchronous processors have a number of advantages, especially in SoC (System on chip) including reduced crosstalk between analog and digital circuits, ease of integrating multi-rate circuits, ease of component reuse and less power consumption as well. This paper deals with the novel design and implementation of such type of asynchronous microprocessor by using VHDL on Xilinx ISE tool wherein it has the capability of handling even IType, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time. |
| Starting Page | 39 |
| Ending Page | 47 |
| Page Count | 9 |
| File Format | PDF HTM / HTML |
| DOI | 10.5815/ijieeb.2018.01.06 |
| Volume Number | 10 |
| Alternate Webpage(s) | http://www.mecs-press.org/ijieeb/ijieeb-v10-n1/IJIEEB-V10-N1-6.pdf |
| Alternate Webpage(s) | https://doi.org/10.5815/ijieeb.2018.01.06 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
