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Implimentation of A 16-bit RISC Processor for Convolution Application
| Content Provider | Semantic Scholar |
|---|---|
| Author | Kumar, B. Rajesh Ravisaketh Kumar, Santha |
| Copyright Year | 2014 |
| Abstract | RISC architecture is used across a wide range of platforms from Cellular phones to super computers.In this paper,a 16bit RISC processor is designed, which utilizes minimum functional units without compromising in performance. The design is based on architectural modification made in the incrementer circuit which is used in program counter.A Low Power Area Efficient carry select adder and a high speed low power modified Wallace tree multiplier has been designed to improving perfomance of ALU in RISC processor. The RISC processor has been realized using Verilog HDL.The individual modules are designed and tested at each level and finally integrated in the top level module.Individual modules, toplevel module are simulated by using Xilinx ISE14.2. Synthesis, power estimation and area estimation is done by using Cadence.The power consumption obtanied is 1174 nw and area is 15041 nm.As against of referace RISC processor which is used Normal Carry select adder and Wallace tree multipler. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ripublication.com/aeee_spl/aeeev4n5spl_03.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
