NDLI: A 16-bit parallel MAC architecture for a multimedia RISC processor

Content Provider	IEEE Xplore Digital Library
Author	Kuroda, I. Murata, E. Nadehara, K. Suzuki, K. Arai, T. Okamura, A.
Copyright Year	1998
Description	Author affiliation: NEC Corp., Kawasaki, Japan (Kuroda, I.)
Abstract	This paper presents a parallel MAC (multiply-accumulation) architecture designed for DSP applications on a 200-MHz, 1.6-GOPS multimedia RISC processor. The datapath architecture of the processor is designed to realize parallel execution of a data transfer and SIMD parallel arithmetic operations. SIMD parallel 16-bit MAC instructions are introduced with a symmetric rounding scheme which maximizes the accuracy of the 18-bit accumulation. This parallel 16-bit MAC instruction on a 64-bit datapath is shown to be efficiently utilized for DSP applications such as convolution in the multimedia RISC processor. By using the parallel MAC instruction with the symmetric rounding scheme, the two-dimensional inverse discrete cosine transform (2D-IDCT) which satisfies IEEE 1180 can be implemented in 202 cycles.
Starting Page	103
Ending Page	112
File Size	536898
Page Count	10
File Format	PDF
ISBN	0780349970
ISSN	15206130
DOI	10.1109/SIPS.1998.715773
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-10-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reduced instruction set computing Digital signal processing Process design Arithmetic Convolution Discrete cosine transforms
Content Type	Text
Resource Type	Article

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