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Design of 16-bit RISC Processor
| Content Provider | Semantic Scholar |
|---|---|
| Author | Gaonkar, Supraj Anitha, Murugesan |
| Copyright Year | 2013 |
| Abstract | The Reduced Instruction Set Computer or RISC is a microprocessor design principle that favours a smaller and simpler set of instructions that all take same amount of time to execute. RISC architecture is used across a wide range of platforms from cellular phones to super-computers. In this paper the behavioural design and functional characteristics of 16bit RISC processor is proposed, which utilizes minimum functional units without compromising in performance. The design is based on Harvard architecture having separate data memory and instruction memory. The instruction word length is 24-bit wide. The processor supports 16 instructions with three addressing modes. It has 16 general purpose registers. Each register can store 16-bit data. The processor has 16-bit ALU capable of performing 11 arithmetical and logical operations. The processor also incorporates a flag register which indicates carry, zero and parity status of the result. All the modules in the design are coded in Verilog. The individual modules are designed and tested at each level of implementation and finally integrated in a top level module by appropriate mapping. The design entry and synthesis is done using Xilinx ISE 10.1 tool and simulation results are verified using Modelsim 10.2. Key words— RISC, 16-bit CPU, Verilog |
| File Format | PDF HTM / HTML |
| Volume Number | 2 |
| Alternate Webpage(s) | https://www.isroset.org/pub_paper/IJSRPAS/ISROSET-IJSRPAP-00068.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
