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Processor realization for application of convolution.
| Content Provider | CiteSeerX |
|---|---|
| Author | Bhirange, Prashant D. Nasre, V. G. Gaikwad, M. A. |
| Abstract | Abstract––Convolution is very important in signal and image processing applications which is used in filter designing. Many algorithms have been proposed in order to accomplish an improved the performance of the filters by using the convolution design. The architecture of the proposed RISC CPU is a uniform 32-bit instruction format, single cycle nonpipelined processor. It has load/store architecture, where the operations will only be performed on registers, and not on memory locations. It follows the classical von-Neumann architecture with just one common memory bus for both instructions and data. A total of 27 instructions are designed in initial development step of the processor. The instruction set consists of Logical, Immediate, Jump, Load, store and HALT type of instruction. The combined advantages RISC processor such as high speed, low power, area efficient and operation-specific design possibilities have been analyzed. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Processor Realization Uniform 32-bit Instruction Format Halt Type Low Power Risc Cpu Initial Development Step Abstract Convolution Memory Location Operation-specific Design Possibility Instruction Set Many Algorithm Convolution Design Area Efficient Classical Von-neumann Architecture Store Architecture Combined Advantage Risc Processor Image Processing Application Common Memory Bus Single Cycle High Speed |
| Content Type | Text |
