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MDC FFT / IFFT Processor with 64-Point using Radix-4 Algorithm for MIMO-OFDM System
| Content Provider | Semantic Scholar |
|---|---|
| Author | Arun Eddy Amana |
| Copyright Year | 2014 |
| Abstract | Human needs with technical de vices are increasing rapidly. In order to meet their requirements the system should be accurate and fast. The fastness and accuracy of a system depends on its intra and inter peripherals/algorithms. In the view of t his, the proposed paper came into existence. MDC, we propose simple memory scheduling methods for input data and output bit/set-reversing, which again results in a full utilization rate in memory usage. It focuses on the development of the Fast Fourier Transform (FFT) algorithm, based on Decimation-InTime (DIT) domain, calle d Radix-4 DIT-FFT algorithm. Verilog is used as a design entity and for simulation Xilinx ISE and modelsim. The synthesis results show that the computation for calculating the 64-point FFT is efficient in terms of speed and area is implemented on UMC 90-nm CMOS technology. This processor can be used in IEEE 802.16 WiMAX and 3G PP long term evolution applications. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ijsetr.com/uploads/365412IJSETR2482-966.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
