Loading...
Please wait, while we are loading the content...
Similar Documents
Implementation of High Speed MDC FFT/IFFT Processor for MIMO-OFDM Systems
| Content Provider | Semantic Scholar |
|---|---|
| Author | Madhavi, Sanikommu Reddy, T. Thammi |
| Copyright Year | 2015 |
| Abstract | The architecture of multipath delay commutator (MDC) and memory scheduling are the basic concepts used to implement fast Fourier transform (FFT) processors with variable length. This FFT processors are used in orthogonal frequency division multiplexing systems, having multiple number of inputs and multiple number of outputs. Depending on this MDC architecture, we implement the FFT/IFFT processor based design which is proposed in this paper. In this design we implement ram, FIFO, input buffer and output sorting buffer. The functional verification and the synthesis is carried out using XILINX and CADENCE EDA tools and shows the reduced delay values. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ijsetr.com/uploads/145263IJSETR5831-882.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
