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Based 64-point Pipelined Fft Using Radix-4 Combined Sdf-mdc
| Content Provider | Semantic Scholar |
|---|---|
| Author | Thabitha, K. Jayakumar, Dontabhaktuni |
| Copyright Year | 2018 |
| Abstract | This paper presents the design of new VLSI based 64-point pipelined Radix-4 FFT architecture named as “64-point pipelined FFT using Radix-4 Combined Single Path Delay Feedback (SDF) Multi path Delay Commutator (MDC) FFT”. As the name itself indicates, the design of proposed FFT architecture is designed with the help of both SDF and MDC structures that have different types of advantages based on their data flow structures. SDF structure has advantages in improving the speed and MDC structure has advantages in reducing the low chip area and lower power consumption. In addition to the developed architecture, Modified Bit Parallel Multiplier (MBPM) has been used in the place of twiddle factor multiplication. When compared to traditional equivalents, the proposed architecture which is used to improve the high processing speed and high performances of FFT processor. Simulation of proposed FFT architectures are evaluated by using ModelSim 6.3C and performances are validated by using Xilinx Planahead Integrated Circuit (IC) vendors. Proposed new circuits will be absolutely used in Orthogonal Frequency Division Multiplexing (OFDM) and Software Defined Radio (SDR) system. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://acadpubl.eu/hub/2018-118-21/articles/21d/73.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
