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Static Quantized Radix-2 FFT/IFFT Processor for Constraints Analysis Static Quantized Radix-2 FFT/IFFT Processor for Constraints
| Content Provider | Hyper Articles en Ligne (HAL) |
|---|---|
| Author | Teymourzadeh, Rozita Abigo, Jim Mok, Vee |
| Copyright Year | 2018 |
| Abstract | Analysis This research work focuses on the design of a high-resolution fast Fourier transform (FFT) /inverse fast Fourier transform (IFFT) processors for constraints analysis purpose. Amongst the major setbacks associated with such high resolution, FFT processors are the high power consumption resulting from the structural complexity and computational inefficiency of floating-point calculations. As such, a parallel pipelined architecture was proposed to statically scale the resolution of the processor to suite adequate trade-off constraints. The quantization was applied to provide an approximation to address the finite word-length constraints of digital signal processing (DSP). An optimum operating mode was proposed, based on the signal-to-quantization-noise ratio (SQNR) as well as the statistical theory of quantization, to minimize the trade-off issues associated with selecting the most application-efficient floating-point processing capability in contrast to their resolution quality. |
| Related Links | https://hal.science/hal-01800754/file/2013D%20Static%20quantised%20radix2%20fast%20Fourier%20transform%20FFT%20inverse%20FFT%20processor%20for%20constraints%20analysis.pdf |
| ISSN | 00207217 |
| Journal | International Journal of Electronics |
| e-ISSN | 13623060 |
| Language | English |
| Publisher | HAL CCSD Taylor & Francis |
| Access Restriction | Open |
| Subject Keyword | DSP DFT FFT quantized IFFT IDFT floating-point |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Science Electrical and Electronic Engineering |
