NDLI: Dataflow object detection system for FPGA-based smart camera

Please wait, while we are loading the content...

Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal–oxide–semiconductor field-effect transistors

Inter-coarse-grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel-stream on coarse-grained reconfigurable architecture-based multi-core architecture

Periodic switching circuit analysis using admittance matrices

Transfer functions of a transformer at different values of coupling coefficient

Two-parallel pipelined fast Fourier transform processors for real-valued signals

Very large scale integration architecture for block-matching motion estimation using adaptive rood pattern search algorithm

Volume 10 (2016) : Issue 3, May

Volume 10 (2016) : Issue 2, Mar

Volume 10 (2016) : Issue 1, Jan

IET Collaborative Intelligent Manufacturing

IET Communications

IET Computer Vision

IET Computers & Digital Techniques

IET Control Theory & Applications

IET Cyber-Physical Systems: Theory & Applications

IET Cyber-Systems and Robotics

IET Electric Power Applications

IET Electrical Systems in Transportation

IET Energy Systems Integration

IET Generation, Transmission & Distribution

IET Image Processing

IET Information Security

IET Intelligent Transport Systems

IET Microwaves, Antennas & Propagation

IET Nanobiotechnology

IET Nanodielectrics

IET Networks

IET Optoelectronics

IET Power Electronics

IET Quantum Communication

IET Radar, Sonar & Navigation

IET Renewable Power Generation

IET Science, Measurement & Technology

IET Signal Processing

IET Wireless Sensor Systems

Micro & Nano Letters

The Journal of Engineering

Dataflow object detection system for FPGA-based smart camera

Content Provider	IET Digital Library
Author	Bourrasset, Cédric Maggiani, Luca Sérot, Jocelyn Berry, François
Abstract	Embedded computer vision based smart systems raise challenging issues in many research fields, including real-time vision processing, communication protocols or distributed algorithms. The amount of data generated by cameras using high resolution image sensors requires powerful computing systems to be processed at digital video frame rates. Consequently, the design of efficient and flexible smart cameras, with on-board processing capabilities, has become a key issue for the expansion of smart vision systems relying on decentralised processing at the image sensor node level. In this context, field programmable gate arrays (FPGA)-based platforms, supporting massive data parallelism, offer large opportunities to match real-time processing constraints compared with platforms based on general purpose processors. In this study, the authors describe the implementation, on such a platform, of a configurable object detection application, reformulated according to the dataflow model of computation. The application relies on the computation of the histogram of oriented gradients and a linear SVM-based classification. It is described using the CAPH programming language, allowing efficient hardware descriptions to be generated automatically from high level dataflow specifications without prior knowledge of hardware description languages such as VHDL or Verilog. Results show that the performance of the generated code does not suffer from a significant overhead compared with handwritten HDL code.
Starting Page	280
Ending Page	291
Page Count	12
ISSN	1751858X
Volume Number	10
e-ISSN	17518598
Issue Number	Issue 4, Jul (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/10/4
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2015.0071
Journal	IET Circuits, Devices & Systems
Publisher Date	2016-07-01
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Camera CAPH Programming Language Communication Protocols Computer Vision Computer Vision And Image Processing Technique Configurable Object Detection Data Flow Analysis Dataflow Object Detection System Digital Video Frame Rates Distributed Algorithm Embedded Computer Vision Field Programmable Gate Array Flexible Smart Cameras FPGA-based Smart Camera Generated Code Hardware Descriptions High Level Dataflow Specifications High Resolution Image Sonsor Image Sonsor Knowledge Engineering Technique Linear SVM-based Classification Logic And Switching Circuit Logic Circuit Massive Data Parallelism Object Detection On-board Processing Optical, Image And Video Signal Processing Oriented Gradients Programming Languages Real Time System Real-time Processing Constraint Real-time Vision Processing Smart Vision System Support Vector Machine
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

YOLOpeds: efficient real-time single-shot pedestrian detection for smart camera applications

Unknown multiple object tracking using 2D lidar and video camera

Real-time object entity detection system for smart surveillance application

Real-Time FPGA-Based Object Tracker with Automatic Pan-Tilt Features for Smart Video Surveillance Systems

High-level dataflow programming for real-time image processing on smart cameras

Robust moving object detection using compressed sensing

Phoning it in

Vision-based inter-vehicle distance estimation for driver alarm system

Dense optical flow based background subtraction technique for object segmentation in moving camera environment

Dataflow object detection system for FPGA-based smart camera

Similar Documents

YOLOpeds: efficient real-time single-shot pedestrian detection for smart camera applications

Unknown multiple object tracking using 2D lidar and video camera

Real-time object entity detection system for smart surveillance application

Real-Time FPGA-Based Object Tracker with Automatic Pan-Tilt Features for Smart Video Surveillance Systems

High-level dataflow programming for real-time image processing on smart cameras

Robust moving object detection using compressed sensing

Phoning it in

Vision-based inter-vehicle distance estimation for driver alarm system

Dense optical flow based background subtraction technique for object segmentation in moving camera environment

Dataflow object detection system for FPGA-based smart camera