NDLI: Heuristic algorithm for periodic clock optimisation in scheduling-based latency-insensitive design

Content Provider	IET Digital Library
Author	Zare, Mahdi Hessabi, Shaahin Goudarzi, Maziar
Abstract	Delay in communication wires causes design iterations in system-on-chip. Latency-insensitive design copes with this issue by encapsulating each core in a shell wrapper and inserting buffers in the wires to separate the design of core from that of communication wires. Scheduling-based latency-insensitive protocol is a methodology which employs shift registers for periodic clock gating of blocks instead of the shell wrappers. In many cases, the bit sequences inside the shift registers are too long and therefore consume a large area. This study presents a heuristic algorithm that optimises the bit sequences and produces them with shorter lengths compared with the existing method. The algorithm steps are described and the accuracy is validated through several synthetic benchmarks as well as real systems. Simulation results show an average 44.7% reduction on the shift registers area and the synthetic analysis in the authors proposed approach show an average 12.8% reduction on the total system area compared with the existing method.
Starting Page	165
Ending Page	174
Page Count	10
ISSN	17518601
Volume Number	9
e-ISSN	1751861X
Issue Number	Issue 3, May (2015)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/9/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2013.0121
Journal	IET Computers & Digital Techniques
Publisher Date	2015-02-06
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Bit Sequences Buffer Insertion Clocks Communication Wires Design Iterations Digital Circuit Design, Modelling And Testing Heuristic Algorithm Integrated Circuit Design Logic And Switching Circuit Logic Circuit Optimisation Optimisation Technique Periodic Clock Gating Periodic Clock Optimisation Scheduling Scheduling-based Latency-insensitive Design Scheduling-based Latency-insensitive Protocol Shell Wrapper Shift Registers Synthetic Analysis System-on-chip
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Fast Heuristic Algorithm for Multidomain Clock Skew Scheduling

Gated-Clock Design of Linear-Feedback Shift Registers

Simple power analysis applied to nonlinear feedback shift registers

Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications

A low-latency asynchronous shift register

An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Synthesis of nonzero clock skew circuits

Analysis of Scheduled Latency Insensitive Systems with Periodic Clock Calculus

Heuristic algorithm for periodic clock optimisation in scheduling-based latency-insensitive design

Similar Documents

A Fast Heuristic Algorithm for Multidomain Clock Skew Scheduling

Gated-Clock Design of Linear-Feedback Shift Registers

Simple power analysis applied to nonlinear feedback shift registers

Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications

A low-latency asynchronous shift register

An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Synthesis of nonzero clock skew circuits

Analysis of Scheduled Latency Insensitive Systems with Periodic Clock Calculus

Heuristic algorithm for periodic clock optimisation in scheduling-based latency-insensitive design