NDLI: Path delay test generation at functional level

Content Provider	IET Digital Library
Author	Bareisa, Eduardas Jusas, Vacius Motiejunas, Kestutis Seinauskas, Rimantas
Abstract	The path delay tests, which are used to test the maximum speed of the circuit, usually are generated at the structural level. The authors suggested the path delay fault test generation approach for non-scan sequential circuits at the functional level. The circuit is considered as a black box model having the primary inputs, primary outputs and state bits. The state bits of the model are transformed into pseudo-primary inputs and pseudo-primary outputs. The circuit is represented as the iterative logic array model, consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles, which has to be chosen before test generation. To assess the length of the path at the functional level they suggested a new criterion. The length of the path is assessed by the number of the sensitive paths connected to the particular input and to the particular output. The experimental results are provided for the ITC'99 benchmark circuits. The generated functional test for path delay faults can be used either on its own if there is no structural test or it can be used as a supplement to the structural test.
Starting Page	135
Ending Page	141
Page Count	7
ISSN	17518601
Volume Number	9
e-ISSN	1751861X
Issue Number	Issue 3, May (2015)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/9/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2013.0096
Journal	IET Computers & Digital Techniques
Publisher Date	2015-02-13
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Automatic Test Pattern Generation Black Box Model Circuit Testing Clock Cycles Combinational Circuit Combinational Logic Digital Circuit Design, Modelling And Testing Functional Level Functional Test Generation Interpolation And Function Approximation ITC99 Benchmark Circuit Iterative Logic Array Model Iterative Method Logic And Switching Circuit Logic Array Logic Circuit Logic Design Method Nonscan Sequential Circuit Numerical Analysis Path Delay Fault Test Generation Approach Path Delay Test Generation Path Length Assessment Pseudoprimary Input Pseudoprimary Output Sequential Circuit State Bits Structural Level
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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