NDLI: System-level assertions: approach for electronic system-level verification

Content Provider	IET Digital Library
Author	Sohofi, Hassan Navabi, Zainalabedin
Abstract	As design of digital systems become more complex and more transistors are incorporated into a single chip, design and verification methodologies moves into higher levels. Now that design at the register transfer level (RTL) has reached its maturity, the focus is shifting to electronic system level (ESL) design tools, languages and methodologies. At the centre of this and perhaps the most challenging are verification methods and tools to use for verifying designs at the ESL. This study presents a new concept of system-level assertions for ESL verification. It also demonstrates an environment for functionally verifying system-level designs using these system-level assertions. The proposed environment adapts existing EDA simulation tools, which are mainly used for RTL design and verification, and utilises them for system-level verification. In this environment, designs are modelled in SystemC-transaction level modelling 2.0, and assertions are written in SystemVerilog. Design and verification parts are connected together using SystemVerilog Direct Programming Interface mechanism, and designs that are described in SystemC are verified against system-level assertions in the course of SystemVerilog simulation.
Starting Page	142
Ending Page	152
Page Count	11
ISSN	17518601
Volume Number	9
e-ISSN	1751861X
Issue Number	Issue 3, May (2015)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/9/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2014.0084
Journal	IET Computers & Digital Techniques
Publisher Date	2014-08-20
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	C Language EDA Simulation Tools Electronic Engineering Computing Electronic System Level Design Tool Electronic System-level Verification ESL Verification Formal Method Formal Verification System-level Assertion SystemC-transaction Level Modelling 2.0 SystemVerilog Direct Programming Interface Mechanism
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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