NDLI: Analysis of cascaded H-bridge multilevel inverter configuration with double level circuit

Content Provider	IET Digital Library
Author	Prabaharan, Natarajan Palanisamy, Kaliannan
Abstract	In this study, a new multilevel inverter configuration which introduces a combination of cascaded H-bridge multilevel inverter with a double level circuit is proposed. The double level circuit is a half-bridge inverter when combined with a cascaded H-bridge multilevel inverter, will increase the output voltage level to nearly twice that of a conventional cascaded H-bridge multilevel inverter. The effectiveness of the proposed configuration is demonstrated with five different cases of cascaded H-bridge multilevel inverter configurations. Phase disposition carriers arrangement with sinusoidal reference has been utilised in pulse width modulation for generating the gating signal of switches to achieve high-quality output voltage waveform. A comparison is carried out with different parameters such as %total harmonic distortion, distortion factor, the maximum voltage step of output voltage level and peak inverse voltage. Analysis of power loss and theoretical calculation of %total harmonic distortion is described. Also, a new method for calculating the overall component count is discussed. As a result, the proposed configuration requires lesser component count for generating higher output voltage level with lower %total harmonic distortion. Selected simulation and experimental results are shown to verify and validate the proposed multilevel inverter configuration.
Starting Page	1023
Ending Page	1033
Page Count	11
ISSN	17554535
Volume Number	10
e-ISSN	17554543
Issue Number	Issue 9, Jul (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-pel/10/9
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-pel.2016.0506
Journal	IET Power Electronics
Publisher Date	2017-03-22
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Cascaded H-bridge Multilevel Inverter Distortion Factor Double Level Circuit Gating Signal Half-bridge Inverter Harmonic Distortion High-quality Output Voltage Waveform Maximum Voltage Step Multilevel Inverter Configuration Peak Inverse Voltage Phase Disposition Carriers Arrangement Power Loss Pulse Width Modulation PWM Invertors Sinusoidal Reference Total Harmonic Distortion
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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