NDLI: Crisscross switched multilevel inverter using cascaded semi-half-bridge cells

Content Provider	IET Digital Library
Author	Arun, Nandagopal Noel, Mathew Mithra
Abstract	A new cascaded multilevel inverter (MLI) is presented with the aim of utilising lesser number of switches, better modularity and reduced voltage stress. The new structure configured under symmetric and asymmetric mode, produces all odd and even voltage levels. This structure comprises semi-half-bridge cells connected in series with crisscross switches to generate any target level for synthesising the sinusoidal output voltage waveform. In extension to the proposed topology, subinverters derived from the proposed MLI are cascaded with an objective to produce more voltage levels with reduced standing voltage. Compared with the cascading H-bridge topology, the proposed MLI and the extended version uses lesser number of semi-conductor switches. The MATLAB R2013b-based simulation results along with the experimental results validate the proposed topology.
Starting Page	23
Ending Page	32
Page Count	10
ISSN	17554535
Volume Number	11
e-ISSN	17554543
Issue Number	Issue 1, Jan (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-pel/11/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-pel.2016.0644
Journal	IET Power Electronics
Publisher Date	2017-07-31
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Asymmetric Mode Cascaded Multilevel Inverter Cascaded Semi Half-bridge Cell Crisscross Switched Multilevel Inverter Crisscross Switches Even Voltage Level Invertors MATLAB R2013b-based Simulation Result MLI Odd Voltage Level Power Electronics Power Semiconductor Device Power Semiconductor Switches Power Supply Reduced Standing Voltage Reduced Voltage Stress Relay And Switches Sinusoidal Output Voltage Waveform Synthesis Supervisory Circuit Symmetric Mode
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Comprehensive review of a recently proposed multilevel inverter

Reconfiguration of semi-cascaded multilevel inverter to improve systems performance parameters

Step-up switched-capacitor module for cascaded MLI topologies

Reliability improvement of transistor clamped H-bridge-based cascaded multilevel inverter

Multilevel voltage source inverter with optimised usage of bidirectional switches

Multi-level inverter with combined T-type and cross-connected modules

Design and implementation of a novel three-phase cascaded half-bridge inverter

Analysis of cascaded H-bridge multilevel inverter configuration with double level circuit

Developed cascaded multilevel inverter topology to minimise the number of circuit devices and voltage stresses of switches

Crisscross switched multilevel inverter using cascaded semi-half-bridge cells

Similar Documents

Comprehensive review of a recently proposed multilevel inverter

Reconfiguration of semi-cascaded multilevel inverter to improve systems performance parameters

Step-up switched-capacitor module for cascaded MLI topologies

Reliability improvement of transistor clamped H-bridge-based cascaded multilevel inverter

Multilevel voltage source inverter with optimised usage of bidirectional switches

Multi-level inverter with combined T-type and cross-connected modules

Design and implementation of a novel three-phase cascaded half-bridge inverter

Analysis of cascaded H-bridge multilevel inverter configuration with double level circuit

Developed cascaded multilevel inverter topology to minimise the number of circuit devices and voltage stresses of switches

Crisscross switched multilevel inverter using cascaded semi-half-bridge cells